Serial parallel analog-to-digital converter using voltage level shifting of a minimum reference voltage

• US 4,214,233 A
• Filed: 06/17/1977
• Issued: 07/22/1980
• Est. Priority Date: 06/17/1977
• Status: Expired due to Term

• Current Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Kreinick, Stephen J., Shaw, Pern, Musa, Fuad H.
• Primary Examiner(s): Sloyan, Thomas J.
• Application Number:
  US05/807,472
• Time in Patent Office: 1,131 Days
• Field of Search: 340/347 M, 340/347 AD, 324/99 D, 307/299 B, 307/360
• US Class Current: 341/156
• CPC Class Codes: H03M 1/1019 by storing a corrected or correction value in a digital look-up table
• CPC Class Codes: H03M 1/682 both converters being of the unary decoded type

Abstract

An analog-to-digital converter includes a first and a second comparator each of which receives an analog input. The first comparator generates a plurality of reference voltages which establish a first continuous range of voltage gaps. The first comparator has a plurality of quantizing outputs, one of which will be at a logical one and the rest of which will be at logical zeros in order to indicate which of the voltage gaps encompasses the analog input voltage. The first comparator also has first and second reference current outputs whose magnitudes are representative of which voltage gap encompasses the analog input voltage and a third reference current output whose magnitude is representative of the voltage gap width. A first encoder receives the quantizing outputs of the first comparator and generates a binary number which represents which of the voltage gaps the analog input voltage is encompassed by and which constitutes the most significant bit group of the binary digital representation of the analog input voltage. The reference current outputs of the first comparator are input to a reference voltage level shifting circuit whose output voltage represents the voltage difference between a first boundary of the voltage gap which encompasses the analog input voltage and the maximum reference voltage value associated with the first comparator. The reference voltage level shifting output voltage is produced concurrently with the action of the first encoder, thereby providing overlapping operations for increased conversion speeds. This shifted reference voltage is provided as an input to a second comparator which compares the analog input with a plurality of internal reference voltages which form a second continuous range of voltage gaps. The second comparator has a plurality of outputs, one corresponding to each of the voltage gaps encompassed by the reference voltages in the second comparator. The second comparator produces a logical one on an output corresponding to the particular voltage gap defined by the shifted reference voltage. A second encoder receives as inputs the outputs of the second comparator and generates a binary output which represents the least significant bit group of the analog input voltage. In combination, the output of the first encoder and the output of the second encoder form a binary digital representation of the analog input voltage, including the most significant bits and the least significant bits thereof.

Claims

1. An analog-to-digital converter comprising:

(a) means for receiving an analog signal;

(b) first comparator means responsive to said analog signal and including

(i) means for providing a first series of reference voltages ranging between a minimum reference voltage and a maximum reference voltage;

(ii) a first plurality of differential comparison circuits, each having associated with it one of said first series of reference voltages and each including means for generating a first increment of current when said analog signal exceeds said associated reference voltage and means for generating a second increment of current when said analog signal is less than said associated reference voltage;

(iii) means responsive to said first and second increments of current for generating a first output signal;

(iv) first current summing means for adding said first increments of current to form a first reference current;

(v) means for providing first and second constant current signals; and

(vi) second current summing means for adding said first reference current and said first constant current signal to produce a second reference current;

(c) first encoder means responsive to said first output signal for producing a first digital number;

(d) a reference voltage level shifting circuit comprising

(i) a current mirror circuit having a first terminal responsive to said second reference current and a second terminal, said current mirror circuit producing at said second terminal a mirror current equal in magnitude to said second reference current; and

(ii) resistance means having a first terminal coupled to said minimum reference voltage and a second terminal coupled to the second terminal of said current mirror circuit and providing a shifted maximum reference voltage;

(e) second comparator means including

(i) means for providing a second series of reference voltages, said means comprising a resistive ladder network having first and second terminals, said first terminal being coupled to said shifted maximum reference voltage, and an operational amplifier having a non-inverting input coupled to said second constant current signal, an output, and an inverting input coupled to said output and to the second terminal of said resistive ladder network; and

(ii) comparison means responsive to said second series of reference voltages and said analog signal for generating a second output signal; and

(f) second encoder means responsive to said second output signal for producing a second digital number.

2. The voltage level shifting circuit as recited in claim 1 wherein the resistance value of said resistance means is R1, and said resistive ladder network comprises 2^L series connected resistors each having a resistance value (R1/2^L), L being a positive integer.

3. The voltage level shifting circuit as described in claim 1 wherein said current mirror circuit further comprises:

means for providing a supply voltage;

first and second resistors of equal resistance value each having a first terminal coupled to said supply voltage and each having a second terminal;

first and second transistors having their respective emitters coupled to the second terminals of said first and second resistors and having their bases connected together, said first transistor having its collector coupled to said second reference current, and said second transistor having its collector coupled to its base; and

a third transistor having its emitter coupled to the collector of said second transistor, having its base coupled t the collector of said first transistor, and having its collector coupled to the second terminal of said resistance means.

4. The analog-to-digital converter as recited in claim 1 wherein the first and second digital numbers represent the most significant and least significant bits, respectively, of the converted analog signal.