Dual microprocessor intelligent programmable process control system with communication link

• US 4,215,398 A
• Filed: 08/24/1978
• Issued: 07/29/1980
• Est. Priority Date: 08/24/1978
• Status: Expired due to Term

• Current Assignee: Siemens Energy & Automation Incorporated (Siemens AG)
• Original Assignee: Texas Instruments, Inc.
• Inventors: Bunyard, Michael L., Burkett, Bobby G.
• Primary Examiner(s): Ruggiero, Joseph F.
• Application Number:
  US05/936,422
• Time in Patent Office: 705 Days
• Field of Search: 364/101, 364/102, 364/100, 364/103, 364/104, 364/107, 364/120, 364/474, 364/200 MS File, 364/900 MS File
• US Class Current: 700/7
• CPC Class Codes: G05B 19/052 Linking several PLC's
• CPC Class Codes: G05B 2219/1159 Image table, memory
• CPC Class Codes: G05B 2219/1161 Signal processing, detect or deliver analog signals
• CPC Class Codes: G05B 2219/1204 Multiprocessing, several plc's, distributed logic control
• CPC Class Codes: G05B 2219/1205 Memory access for different processors, memory arbitration, mailbox
• CPC Class Codes: G05B 2219/15048 Microprocessor
• CPC Class Codes: G05B 2219/15127 Bit and word, byte oriented instructions, boolean and arithmetic operations

Abstract

An intelligent programmable process control system for controlling industrial processing and manufacturing equipment and the like utilizes a unique system of cooperating dual microprocessors. A digital microprocessor is utilized for digital computation and for controlling the analog portion of the processing equipment, and a boolean microprocessor is utilized for sequencing and for controlling the on/off states of devices located along the process in response to the on/off states of sensors located along the process according to a sequence of boolean logic functions. The digital microprocessor has overall supervisory control. Common memory provides a communication link between the two microprocessors. An arbitration circuit for resolving simultaneous or phased access to memory by the two microprocessors is provided. In addition, a circuit is provided for accomplishing parallel digital input/output functions, again accessible by both microprocessors. In one embodiment, means for linking arithmetic functions and non-arithmetic logic functions within a boolean-type instruction set is provided.

Claims

1. An intelligent programmable process control system responsive to the on/off states of sensors located along a process for controlling the on/off states of controllable devices located along said process comprising:

(a) a first microprocessor for performing digital operations and arithmetic computations;

(b) a second microprocessor for scanning and executing a sequence of boolean logic functions asynchronously with respect to the processing of said first microprocessor;

(c) a random access memory, said first and second microprocessor each being coupled to said random access memory to provide a first coupling therebetween to communicate with each other via selectively addressed memory locations of said random access memory;

(d) an image register for storing input bits representative of the on/off states of said sensors and output bits representative of the on/off states of said controllable devices, said second microprocessor being coupled to said image register for executing said sequence of boolean logic functions in accordance with the states of said input bits to generate said output bits; and

(e) other means coupling said second microprocessor to said first microprocessor whereby said second microprocessor signals said first microprocessor to perform digital operations and arithmetic computations for said second microprocessor, the results of operations and computations for said second microprocessor being communicated to said second microprocessor via said random access memory and said second microprocessor generating output bits for controlling the on/off states of controllable devices along said process based upon the results of the operations and computations performed by said first microprocessor for said second microprocessor.

2. The intelligent programmable process control system according to claim 1, wherein said second microprocessor includes means for signalling said first microprocessor whenever digital operations and arithmetic computations are required by said second microprocessor.

3. The intelligent programmable process control system according to claim 1 wherein said first microprocessor includes means for signalling said second microprocessor when the results of requested digital operations and arithmetic computations have been completed by said first microprocessor

4. The intelligent programmable process control system according to claim 1 wherein said second microprocessor includes means for generating the address of said random access memory at which said results are to be stored.

5. The intelligent programmable process control system according to claim 1 wherein said first microprocessor has supervisory control over said second microprocessor.

6. The intelligent programmable process control system according to claim 1 wherein said image register means includes means for storing communication register flag bits, said first and second microprocessor being coupled to said image register means for transmitting and receiving communication register flag bits.

7. The intelligent programmable process control system recording to claim 6 including priority logic circuit means for resolving access requests by said first and second microprocessors to said image register.

8. The intelligent programmable process control system according to claim 7 wherein said priority logic circuit means is coupled to and controlled by a control signal from said second microprocessor means.

9. The intelligent programmable process control system according to claim 8 wherein said priority logic circuit includes:

(a) access request signal means coupling said first microprocessor to said second microprocesor for providing an access request signal to said second microprocessor when said first microprocessor requires access to said second image register, and

(b) access enable means coupling said second microprocessor means to said first microprocessor means and to said image register, said second microprocessor generating said control signal to enable said image register to communicate with said first microprocessor and to indicate to said first microprocessor that it is relinquishing control to said first microprocessor.

10. The intelligent programmable process control system according to claim 6 wherein said first and second microprocessors additionally communicate with each other via selected flag bits of said image register.

11. The intelligent programmable process control system according to claim 1 including a communication register coupled to said image register for transmitting said input and output bits between said image register means and said sensors and controllable devices, respectively.

12. The intelligent programmable process control system according to claim 11 wherein data is transferred serially between said image register and said communication register.

13. The intelligent programmable process control system according to claim 11 wherein data is transferred between said image register and said communication register at the end of each scan of said sequence of boolean logic functions by said second microprocessor.

14. The intelligent programmable process control system according to claim 1 wherein said second microprocessor remains in an idle state while said first microprocessor performs digital operations and arithmetic computations for said second microprocessor.

15. The intelligent programmable process control system according to claim 1 including an arbitration circuit for resolving simultaneous and phased memory requests by said first and second microprocessors to said random access memory.

16. The intelligent programmable process control system according to claim 15 wherein said microprocessors each include request flag signal means coupled to said circuit for requesting access to said random access memory and ready flag signal receiving means coupled to said circuit for enabling said microprocessor to access said memory.

17. The intelligent programmable process control system according to claim 16 wherein said circuit includes means for enabling the first requesting microprocessor when said requests are phased requests and for enabling said second microprocessor when said requests are simultaneous.

18. The intelligent programmable process control system according to claim 16 wherein said microprocessor are placed in an idle condition after requesting memory access until said ready flag signal is received.

22. The intelligent programmable process control system according to claim 16 wherein said first microprocessor has supervisory control over said second microprocessor.

28. The intelligent programmable process control system according to claim 16 including a communication register coupled to said image register for transmitting said input and output bits between said image register means and said sensors and controllable devices, respectively.

29. The intelligent programmable process control system according to claim 22 including a communication register coupled to said image register for transmitting said input and output bits between said image register means and said sensors and controllable devices, respectively.

30. The intelligent programmable process control system according to claim 22 wherein data is transferred between said image register and said communication register at the end of each scan of said sequence of boolean logic functions by said second microprocessor.

31. The intelligent programmable process control system according to claim 16 including an arbitration circuit for resolving simultaneous and phased memory requests by said first and second microprocessors to said random access memory.

19. An intelligent programmable process control system responsive to the states of sensors located along the process for controlling the states of controllable devices located along said process comprising:

(a) a first microprocessor means for performing arithmetic and other computations including relatively complex digital operations, said first microprocessor means including interrupt request input means for interrupting the operations of said first microprocessor means;

(b) a second microprocessor means for scanning and executing a sequence of boolean logic functions independent of the operation of said first microprocessor means, said second microprocessor means including control input means for restarting the operation of said second microprocessor;

(c) a random access memory, said first and second microprocessor each means being coupled to said random access memory provide a first coupling therebetween to communicate with each other via selectively addressed memory locations of said random access memory;

(d) an image register means for storing input bits representative of the states of said sensors and output bits representative of the states of said controllable devices said second microprocessor being coupled to said image register for executing said sequence of boolean functions in accordance with the states of said input bits to generate said output bits;

(e) means coupling said second microprocessor other means to the interrupt input means of said first microprocessor means for transmitting interrupt requests to said first microprocessor for execution of arithmetic computations, and other complex operations beyond the capability of said second microprocessor means, said second microprocessor being in an idle state when transmitting an interrupt request to said first microprocessor; and

(f) means coupling said first microprocessor to the control input means of said second microprocessor controlling the restarting of said second microprocessor.

20. The intelligent programmable process control system according to claim 19 wherein said first microprocessor restarts said second microprocessor via said control input means when the requested arithmetic computation or other complex operation requested by said second microprocessor has been completed by said first microprocessor.

21. The intelligent programmable process control system according to claim 20 wherein said second microprocessor includes means for indicating to said first microprocessor the address of said random access memory at which said results are to be stored.

23. The intelligent programmable process control system according to claim 20 wherein said image register means includes means for storing communication register flag bits, said first and second microprocessor being coupled to said image register means for transmitting and receiving communication register flag bits.

24. The intelligent programmable process control system according to claim 23 wherein said first and second microprocessors additionally communicate with each other via selected flag bits of said image register.

25. The intelligent programmable process control system according to claim 23 including priority logic circuit means for resolving access requests by said first and second microprocessors to said image register.

26. The intelligent programmable process control system according to claim 25 wherein said priority logic circuit means is coupled to and controlled by a control signal from said second microprocessor means.

27. The intelligent programmable process control system according to claim 26 wherein said priority logic circuit includes:

(a) access request signal means coupling said first microprocessor to said second microprocessor for providing an access request signal to said second microprocessor when said first microprocessor requires access to said image register, and

(b) access enable means coupling said second microprocessor means to said first microprocessor means and to said image register, said second microprocessor generating said control signal to enable said image register to communicate with said first microprocessor and to indicate to said first microprocessor that it is relinquishing control to said first microprocessor.

32. The intelligent programmable process control system according to claim 25 wherein said microprocessors each include request flag signal means coupled to said circuit for requesting access to said random access memory, and ready flag signal receiving means coupled said circuit for enabling said microprocessor to access said memory.

33. The intelligent programmable process control system according to claim 26 wherein said circuit includes means for enabling the first requesting microprocessor when said requests are phased requests and for enabling said second microprocessor when said requests are simultaneous.

34. The intelligent programmable process control system according to claim 26 wherein said microprocessors are placed in an idle condition after requesting memory access until said ready flag signal is received.