Selective chemical sensitive FET transducer
First Claim
1. A chemical sensitive field-effect transistor device which comprises:
- an elongated semiconductor substrate having one surface formed with a plurality of diffusion layers, said substrate constituted by a reduced width portion extending from one of the opposed ends of the substrate to a substantially intermediate portion thereof and an enlarged width portion extending from the substantially intermediate portion to the other of the opposed ends thereof,a gate region defined between the diffusion layers on the surface of said elongated substrate and adjacent the free end of the reduced width portion thereof,electrodes electrically connected to the respective diffusion layers at a position adjacent the opposite end of said diffusion layers remote from said gate region,source and drain regions formed on the surface portion of said substrate where the gate region is formed and extends between the reduced end enlarged width portions of said substrate,a double layered structure consisting of a layer of SiO2 and an electrically insulating layer of Si3 N4 overlaying said SiO2 layer, said double layered structure covering substantially the reduced width portion of said substrate in its entirety, and said double layered structure covers the enlarged portion of said substrate at its opposed surfaces while the opposed side faces of the enlarged width portion are uncovered to allow the substrate to be exposed to the outside, said electrically insulating layer of said double layered structure having an impermeability to a solution containing a chemical substance which may affect the electric field developed in an electroconductive channel defined between the diffusion layers at the gate region.
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Accused Products
Abstract
A selective chemical sensitive field-effect transistor device for use in detection and measurement of chemical properties of substances to which the device is exposed is disclosed. The chemical sensitive FET device comprises a semiconductor substrate, at least one pair of spaced apart diffusion layers formed on one surface of the semiconductor substrate and forming source and drain regions, respectively, and a double layer structure consisting of a silicon oxide layer and an electrically insulating layer overlaying the silicon oxide layer. A gate region located on a portion of the surface of the semiconductor substrate between the diffusion layers is overlaid with a chemical selective membrane adapted to interact with certain substances. A method for the manufacture of the above described FET device is also disclosed.
77 Citations
11 Claims
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1. A chemical sensitive field-effect transistor device which comprises:
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an elongated semiconductor substrate having one surface formed with a plurality of diffusion layers, said substrate constituted by a reduced width portion extending from one of the opposed ends of the substrate to a substantially intermediate portion thereof and an enlarged width portion extending from the substantially intermediate portion to the other of the opposed ends thereof, a gate region defined between the diffusion layers on the surface of said elongated substrate and adjacent the free end of the reduced width portion thereof, electrodes electrically connected to the respective diffusion layers at a position adjacent the opposite end of said diffusion layers remote from said gate region, source and drain regions formed on the surface portion of said substrate where the gate region is formed and extends between the reduced end enlarged width portions of said substrate, a double layered structure consisting of a layer of SiO2 and an electrically insulating layer of Si3 N4 overlaying said SiO2 layer, said double layered structure covering substantially the reduced width portion of said substrate in its entirety, and said double layered structure covers the enlarged portion of said substrate at its opposed surfaces while the opposed side faces of the enlarged width portion are uncovered to allow the substrate to be exposed to the outside, said electrically insulating layer of said double layered structure having an impermeability to a solution containing a chemical substance which may affect the electric field developed in an electroconductive channel defined between the diffusion layers at the gate region. - View Dependent Claims (2, 3, 4, 5, 7, 8, 9, 10, 11)
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6. A chemical sensitive field-effect transistor device which comprises:
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an elongated semiconductor substrate made of silicon having a predetermined doping polarity, said substrate being constituted by a reduced width portion extending from one of the opposed ends of the substrate to a substantially intermediate portion thereof and an enlarged width portion extending from the substantially intermediate portion to the other of the opposed ends thereof, a plurality of elongated, spaced apart diffusion layers extending lengthwise of said semiconductor substrate and located at one surface of said substrate, said diffusion layers having a doping polarity opposite to that of the semiconductor substrate, a surface region of said semiconductor substrate which is located between the diffusion layers adjacent the free end of the reduced width portion of said substrate being defined as a gate region, an electroconductive channel stopper layer formed on said surface region of the semiconductor substrate and extending between the diffusion layers excepting a position adjacent the gate region, said channel stopper layer having a doping polarity opposite to that of the diffusion layers, source and drain regions formed on the surface portion of the substrate where the gate region is formed and extends between the reduced and enlarged width portions of said substrate, a double layered structure consisting of a layer of silicon dioxide (SiO2) and an electrically insulating layer of silicon nitride (Si3 N4) external to said silicon dioxide layer and having an impermeability to a solution containing a chemical substance which may, when the device is exposed thereto, affect the electric field developed in an electroconductive channel defined between the diffusion layers at the gate region, overlaying the surface area of the semiconductor substrate such that at the reduced width portion of the substrate it is entirely covered by said double layered structure, whereas the enlarged width portion of the substrate is covered with said double layered structure at its opposed surfaces while the opposed side faces of the enlarged width portion are uncovered to allow the substrate to be exposed to the outside, and source and drain electrodes positioned through the electrically insulating layer and electrically connected to the respective diffusion layers at a position adjacent the opposed end of said diffusion layers remote from said gate region.
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Specification