Integrated logic circuit having interconnections of various lengths between field effect transistors of enhancement and depletion modes

• US 4,218,693 A
• Filed: 01/09/1978
• Issued: 08/19/1980
• Est. Priority Date: 01/17/1977
• Status: Expired due to Term

• Current Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Original Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Inventors: Aldhous, Christopher J., Gee, Lawrence F., Jarvis, Denis B.
• Primary Examiner(s): Munson, Gene M.
• Application Number:
  US05/868,052
• Time in Patent Office: 953 Days
• Field of Search: 357/23, 357/41, 357/45, 307/304
• US Class Current: 326/102
• CPC Class Codes: H01L 27/0883 Combination of depletion and enhancement field effect transistors
• CPC Class Codes: H03K 19/096 Synchronous circuits, i.e. using clock signals H03K19/01728, H03K19/01855 take precedence
• CPC Class Codes: H10B 20/00 Read-only memory [ROM] devices

Abstract

An integrated logic circuit includes an array of insulated gate field effect transistors formed at the crossings of a plurality of substantially parallel first conductor tracks which form the transistor gate electrodes and a plurality of substantially parallel strip-shaped surface regions which form the source and drain electrode regions of the transistors. The field effect transistors of the device include a first group of transistors having a first threshold voltage and a second group of transistors having a second threshold voltage different from the first. In order to make a more compact, easily-designed and easily-manufactured circuit, the conductor tracks and the strip-shaped surface regions form a nonuniform array in which the track and surface regions need not all be of the same length. Further efficiencies are achieved by branching the strip-shaped surface regions where appropriate to implement the desired logic combination.

Claims

1. An integrated circuit for the generation of at least one logic combination of applied logic input signals in a two-state logic system and comprising a semiconductor body having a part mainly of a first conductivity type, an array of insulated gate field effect transistors formed in said part and having gate electrodes self-registered with source and drain electrode regions, and a plurality of substantially parallel first conductive tracks which comprise the transistor gate electrodes and a plurality of substantially parallel strip-shaped surface regions of a second conductivity type opposite to that of the first which adjoin a surface of the body and cross the first conductive tracks, said transistors being formed at the crossings, said surface regions comprising the source and drain electrode regions of said transistors, a first group of the transistors being transistors of a first form having a first threshold voltage and a second group of the transistors being transistors of a second form having a second threshold voltage different from the first, said logic input signals in operation being applied to the gate electrodes of the transistors of one of said first and second groups of transistors, said logic combination to be generated being predetermined by the crossings and the form of transistor present at each such crossing and by the interconnections of transistors of said one of said first and second groups via the second conductivity type strip-shaped surface regions, the array being a nonuniform array in which at least one of the plurality first conductive tracks and the plurality of strip-shaped surfaces regions are not all of the same length, said logic combination further being predetermined by further interconnections formed within the array, and said further interconnections comprising at least a branching of a selected strip-shaped region.

2. An integrated circuit as claimed in claim 1, in which said plurality of first conductive tracks extends as a group of lines at least partly on insulating material on said body surface and substantially parallel in a first direction and said plurality of substantially parallel strip-shaped surface regions of the second conductivity type extends as a group of lines substantially parallel in a second direction which is substantially at right angles to the first direction, said strip-shaped surface regions of the second conductivity type having discontinuities at the areas of the crossings, said first and second threshold voltages being such that the transistors of the second group are conducting in both logic states and the transistors of the first group are conducting only in one logic state, said logic input signals in operation being applied to the gate electrodes of the transistors of the first group, said logic combination to be generated being determined by the interconnection pattern of the first group of transistors, said interconnection pattern comprising the series connection of the main current path of each first group transistor in a common line extending in said second direction and provided by the strip-shaped surface region associated with said line and the main current path of each second group transistor in said line, and said interconnection pattern further comprising the connection of the main current paths of at least one first group transistor in different lines extending in said second direction, the lines in at least one of said two groups of lines being of a plurality of different lengths and said further interconnections comprising further second conductivity type strip-shaped surface regions extending in a direction substantially parallel to the first direction.

3. An integrated circuit as claimed in claim 2, wherein the interconnection pattern further comprises second conductive tracks provided within the array which extend on an insulating material and are separated from the first conductive tracks by said insulating material where overlying said first conductive tracks, the second conductive tracks forming conductive connections via apertures in the insulating material to at least one of the first conductive tracks and the opposite conductivity type surface regions.

4. An integrated circuit as claimed in claim 3, wherein the second conductive tracks are of aluminum.

5. An integrated circuit as claimed in claim 2, wherein the lines of first conductive tracks extending in said first direction are of a plurality of different lengths and the lines of strip-shaped regions extending in said second direction are of a plurality of different lengths.

6. An integrated circuit as claimed in claim 2, wherein a single first conductive track is present in more than one of said lines extending in said first direction.

7. An integrated circuit as claimed in claim 2, wherein the first conductive tracks in the first direction and the strip-shaped opposite conductivity type surface regions in the second direction are provided along the lines of a grid with the transistor structures at the crossings being present at grid points.

8. An integrated circuit as claimed in claim 2, wherein the further opposite conductivity type surface regions within the array are arranged substantially along parts of grid lines where there are no first conductive tracks.

9. An integrated circuit as claimed in claim 1, wherein the transistors of said first group are enhancement transistors and the transistors of said second group are depletion transistors.

10. An integrated circuit as claimed in claim 1, wherein the first conductive tracks are of polycrystalline silicon.

11. An integrated circuit as claimed in in claim 1, wherein the integrated circuit comprises a logic system having clock controlled flip-flops with combinatorial logic circuit parts connected to the flip-flops, the combinatorial logic circuit parts being realized within the array of transistors, the interconnections between the flip-flops and the interconnections of the transistors to form the combinatorial logic circuit parts being commonly associated and defined within the array.