Control circuit for modifying contents of packet switch random access memory

• US 4,218,756 A
• Filed: 06/19/1978
• Issued: 08/19/1980
• Est. Priority Date: 06/19/1978
• Status: Expired due to Term

• Current Assignee: Bell Telephone Laboratories, Inc. (Nokia Corporation)
• Original Assignee: Bell Telephone Laboratories, Inc. (Nokia Corporation)
• Inventors: Fraser, Alexander G.
• Primary Examiner(s): Zache, Raulfe B.
• Application Number:
  US05/916,705
• Time in Patent Office: 792 Days
• Field of Search: 364/200 MS File, 364/200, 364/900
• US Class Current: 711/201
• CPC Class Codes: H04L 12/56 Packet switching systems

Abstract

The information in the header portion of a data packet, which header includes the old module and channel numbers, is used to access locations in a random access memory which contain new module and channel numbers or words that identify the packet routing. To convert the "virtual" address defined by the old module and channel numbers to a physical address, the module number accesses a memory word which is combined with the channel number to produce a single physical address number. When the information stored in the memory is to be changed, the header has special module and channel numbers and the following data includes a "write" command word, address data and information data. The special header words access a memory word which enables the writing of the information data into memory locations selected by the address data. A "read" command word in the packet inserts the word accessed by the address data into the packet.

Claims

1. In a control system for bursts of data, each data burst including a header portion and a subsequent data portion, a random access memory system (107) having means for reading out data from addressed ones of storage locations in the memory and means (101, 103, 106, 108, 109) responsive to data information in the header portion for addressing the storage locations and for modifying the header portion with the data thereby read out of the addressed storage locations, characterized by

means (106, 112, 113WT, 114, 116, 117, 118) responsive to certain of the data read out of the addressed storage locations for writing data from the data portion of the data burst into memory storage locations addressed by an address part of the data portion, the writing means being enabled by predetermined command data in the data portion.

2. In a control system, in accordance with claim 1, and further including means (112, 113RD, 114, 115) responsive to other predetermined command data in the data portion for disabling the writing means and for registering data read out of the storage locations address by the address part.

3. In a control system, in accordance with claim 2, and further including means (102, 105) for inserting the registered data into the data portion part of the data burst.

4. In a control system for packets of data, each data packet having a plurality of address envelopes and a plurality of data envelopes, a random access memory (107) having an address input for selecting storage locations in the memory and a data output for reading out the data stored in the selected storage locations, and means (101, 106) for applying an initial one of the address envelopes to the address input, Characterized by

means (106, 108, 109) for modifying an address envelope subsequent to the initial one with the data read out in response to the application of the initial envelope and for applying the modified envelope to the address input, and

means (106, 112, 113WT, 114, 116, 117, 118) responsive to data read out in response to the application of the modified envelope for writing a portion of the data in the subsequent data envelopes into selected storage locations of the memory.

5. In a control system, in accordance with claim 4, wherein the writing means includes means (106) for concurrently applying another portion of the data in the data envelopes to the address input to define the selected storage locations written into.

6. In a control system for packets of data, each data packet having a plurality of address envelopes and a plurality of data envelopes, a random access memory (107) having an address input for selecting storage locations in the memory and a data output for reading out the data stored in the selected storage locations, and means (101, 106) for applying an initial one of the address envelopes to the address input, Characterized by

means (106, 108, 109) for modifying an address envelope subsequent to the initial one with the data read out in response to the application of the initial envelope and for applying the modified envelope to the address input and

means (106) for applying a portion of the data in the subsequent data envelopes to the address input, and

means (112, 113R, 114, 115) responsive to the data read out in response to the application of the modified envelope for registering the data read out in response to the application of the data portion.