VMOS Mesa structure and manufacturing process

• US 4,219,835 A
• Filed: 02/17/1978
• Issued: 08/26/1980
• Est. Priority Date: 02/17/1978
• Status: Expired due to Term

• Current Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Original Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Inventors: Altiery, Anthony S., van Loon, Paul G. G., Kay, Steeve T. S.
• Primary Examiner(s): Wojciechowicz, Edward J.
• Application Number:
  US05/878,685
• Time in Patent Office: 921 Days
• Field of Search: 357/22, 357/23, 357/55, 357/53, 357/56
• US Class Current: 257/330
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: Y10S 148/028 Dicing
• CPC Class Codes: Y10S 148/051 Etching
• CPC Class Codes: Y10S 148/053 Field effect transistors fets
• CPC Class Codes: Y10S 148/085 Isolated-integrated
• CPC Class Codes: Y10S 257/914 Polysilicon containing oxygen, nitrogen, or carbon, e.g. sipos

Abstract

A V-groove metal oxide semiconductor field effect transistor (V-MOSFET) including a body of semiconductor material having three plane regions defining two plane rectifying junctions. A V-groove extends into said body through said two junctions from one surface. The plane region at said surface comprises the source, the intermediate plane region, the channel, and the other region, the drain. A gate electrode is formed over an insulating layer in said groove, a source electrode connects to said source and channel regions and a drain electrode is connected to said drain region. A moat surrounds said transistor and penetrates the source and channel regions and a field electrode is disposed over an insulating layer covering the moat wall.

Claims

1. A V-groove metal oxide semiconductor field effect transistor comprising a body of semiconductor material including a substrate of one conductivity type, a first region of opposite conductivity type forming a first planar rectifying junction with said substrate, a second region of said one conductivity type forming a second planar junction with the first region, a V-groove in said body extending through said first and second junctions, an insulating layer formed on the walls of said groove and a conductive layer formed on said insulating layer at least adjacent the inclined edges of said first region to form a gate electrode, a groove surrounding said V-groove to form a mesa with side walls, said first and second junctions extending to said side walls, an insulating layer disposed on the surface of said device and on the side walls, and a metal layer disposed on said insulating layer to form a field electrode, a source-body electrode extending through said second region and contacting said first and second regions adjacent said groove, and a metal drain electrode contacting said substrate.

2. A field effect transistor as in claim 1 in which said source-body electrode contacting said first and second regions is formed by alloying into said body through said second junction.

3. A field effect transistor as in claim 1 in which said source-body electrode contacting said first and second regions is formed by a V-groove which extends through said second junction and a metal layer formed on the surface of said groove.

6. A field effect transistor as in claim 1 in which said means forming ohmic contact to said first and second region is formed by alloying into said body through said second junction.

7. A field effect transistor as in claim 1 in which said means forming ohmic contact to said first and second regions is formed by a V-groove which extends through said second junction and a metal layer formed in said groove.

4. A field effect transistor including a body having a substrate of one conductivity type, first and second contiguous regions of opposite and the same conductivity type respectively forming a first planar rectifying junction with said substrate and a second rectifying junction with one another, a V-groove extending into said body through said first and second junctions, a metal-oxide gate electrode formed in said groove, a groove surrounding said V-groove to form a mesa with side walls to which said first and second junctions extend, a metal-oxide field electrode formed on said side walls, a source-body electrode extending through said second junction and forming ohmic contact with said first and second regions and a drain electrode contacting said body.

5. A V-groove metal-oxide semiconductor field effect transistor comprising a body of semiconductor material including a substrate of one conductivity type, a first region of opposite conductivity type forming a first planar rectifying junction with said substrate, a second region of said one conductivity type forming a second planar rectifying junction with the first region, a V-groove in said body extending through said first and second junctions, a groove surrounding said V-groove to form a mesa with side walls, an insulating layer formed on the walls of said groove and the surface and the side walls, a conductive layer formed on said insulating layer extending into said groove at least adjacent the inclined edges of said first region, a conductive layer on the side walls of said mesa and connected to means forming ohmic contact to said first and second regions through said second region adjacent said groove, and a metal drain electrode forming ohmic contact to said substrate.

8. The method of forming a V-groove metal oxide field effect transistor comprising the steps of selecting a body of semiconductor material of one conductivity type, said body having first and second major surfaces, forming at one major surface of said body a first region of opposite conductivity type to form a planar junction with the body forming a second region of the same conductivity type to form a second planar junction with the first region forming on said major surface an oxide mask having a window of predetermined width and a second surrounding opening of predetermined width to expose selected portions of said surface, etching said exposed surfaces until a V-groove is formed in said body at said windows to extend through said first and second junctions, and a surrounding groove is formed to define a mesa, removing the oxide mask, forming a gate oxide on the surface of said device to extend into said groove and on the walls of said mesa, providing a metal layer extending into said groove to form a gate electrode and a metal layer on the walls of said mesa to provide a field electrode, forming a source-body electrode which extends into said body from said one surface to form ohmic contact to said first and second layers, and forming a drain contact to the other surface of the body.

9. A method of forming a V-groove metal-oxide field effect transistor as in claim 8 in which said source-body contact is formed by forming a window in said gate oxide and alloying into said body through said window.

10. The method of forming a V-groove metal oxide field effect transistor as in claim 8 in which said source-body contact is formed by forming a second window of predetermined width in said oxide mask whereby during said etching a second V-groove is formed extending through said second region into said first region of said second window and providing a metal layer in said second V-groove to contact the first and second regions.