Circuit arrangement for improving accuracy of angular measurements in radar systems

• US 4,220,953 A
• Filed: 06/26/1978
• Issued: 09/02/1980
• Est. Priority Date: 06/27/1977
• Status: Expired due to Term

• Current Assignee: Thomson-CSF
• Original Assignee: Thomson-CSF
• Inventors: Carre, Roland
• Primary Examiner(s): Hubler, Malcolm F.
• Application Number:
  US05/918,791
• Time in Patent Office: 799 Days
• Field of Search: 343/16 M, 343/7 A, 343/100 LE
• US Class Current: 342/94
• CPC Class Codes: G01S 13/4427 with means for eliminating the target-dependent errors in angle measurements, e.g. glint, scintillation effects
• CPC Class Codes: G01S 13/685 using simultaneous lobing techniques

Abstract

To improve the accuracy of angular measurements in a radar system by suppressing noise due to target glint, an angular-deviation signal ε derived from the output signals Σ and Δ of a sum channel and a difference channel is gated so as to be read only when the sum signal Σ is at or near a maximum. In a more elaborate embodiment, passage of the deviation signal ε is also blocked when a quadrature-deviation signal εq, likewise derived from the sum and difference signals Σ and Δ, has an absolute magnitude above a preferably adjustable threshold.

Claims

1. A circuit arrangement for improving the accuracy of angular measurements in a radar system with a first reception channel emitting a sum signal Σ

, a second reception channel emitting a difference signal Δ

, and circuitry connected to said reception channels for deriving therefrom an angular-deviation signal ε

appearing on an output thereof, comprising;

peak-detection means connected to said first reception channel for generating a succession of enabling pulses each coinciding with a period close to an instant at which the slope of said sum signal Σ

changes from positive to negative values; and

gating means connected to said output and provided with a control input connected to said peak-detection means for passing said angular-deviation signal ε

only in the presence of one of said enabling pulses.

2. A circuit arrangement as defined in claim 1 wherein said peak-detection means comprises differentiation means for determining said slope, sign-detecting means connected to said differentiation means for generating a square wave changing in polarity with a sign change of said slope, edge-detecting means connected to said sign-detecting means for emitting a spike upon each changeover of said slope from positive to negative values, and pulse-shaping means connected to said edge-detecting means for converting each of said spikes into an enabling pulse of predetermined width.

5. A circuit arrangement as defined in claim 1, 3 or 4 wherein said peak-detection means comprises double-differentiation means for determining the time derivative of said slope and sign-detecting means connected to said double-differentiation means for deriving said unblocking pulses from positive peaks of said time derivative.

3. A circuit arrangement for improving the accuracy of angular measurements in a radar system with a first reception channel emitting a sum signal Σ

, a second reception channel emitting a different signal Δ

, and circuitry connected to said reception channels for deriving therefrom an angular-deviation signal ε and

a quadrature-deviation signal ε

q respectively appearing on a first and a second output thereof, comprising;

peak-detection means connected to said first reception channel for generating a succession of enabling pulses each coinciding with a period close to an instant at which the slope of said sum signal Σ

changes from positive to negative values;

comparison means connected to said second output for deriving a succession of unblocking pulses from those portions of said quadrature-deviation signal ε

q whose absolute values lie below a predetermined threshold; and

gating means connected to said output and provided with a control input connected to said peak-detection means and to said comparison means for passing said angular-deviation signal ε

only during coincidence of one of said enabling pulses with one of said unblocking pulses.

4. A circuit arrangement as defined in claim 3 wherein said comparison means comprises a comparator preceded by a full-wave rectifier and provided with a reference terminal for receiving a selected threshold-determining signal.

6. A circuit arrangement as defined in claim 3 or 4 wherein said circuitry includes an amplitude/phase detector with an input connected directly to said second channel and another input connected via a 90°

phase shifter to said first channel, said second output being an output of said amplitude/phase detector.

7. A circuit arrangement as defined in claim 3 or 4 wherein said circuitry includes a first arithmetic circuit connected to said reception channels for additively combining said sum and difference signals Σ

and Δ

, a second arithmetic circuit connected to said reception channels for subtractively combining said sum and difference signals Σ and

Δ

, and an amplitude/phase detector with input connections to both said arithmetic circuits, said second output being an output of said amplitude/phase detector.