Multilayered glass-ceramic substrate for mounting of semiconductor device

• US 4,221,047 A
• Filed: 03/23/1979
• Issued: 09/09/1980
• Est. Priority Date: 03/23/1979
• Status: Expired due to Term

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Tummala, Rao R., Narken, Bernt
• Primary Examiner(s): Fisher, Richard V.
• Application Number:
  US06/023,113
• Time in Patent Office: 536 Days
• Field of Search: 65/33, 65/18, 65/60 A, 65/60 C, 264/61, 427/89, 427/125, 29/626, 29/625
• US Class Current: 29/840
• CPC Class Codes: H01L 21/4857 Multilayer substrates multilayer metallisation on monolayer substrate H01L21/4846
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 23/15 Ceramic or glass substrates H01L23/142, H01L23/145, H01L23/147 take precedence
• CPC Class Codes: H01L 23/5383 Multilayer substrates H01L23/5385 takes precedence; multilayer metallisation on monolayer substrates H01L23/538
• CPC Class Codes: H01L 2924/01014 Silicon [Si]
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/15312 being a pin array, e.g. PGA
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H05K 1/0306 Inorganic insulating substrates, e.g. ceramic, glass
• CPC Class Codes: H05K 1/112 directly combined with via connections
• CPC Class Codes: H05K 2201/09509 Blind vias, i.e. vias having one side closed
• CPC Class Codes: H05K 2203/0733 Method for plating stud vias, i.e. massive vias formed by plating the bottom of a hole without plating on the walls
• CPC Class Codes: H05K 3/108 by semi-additive methods; masks therefor characterised by metallic etch mask H05K3/062; electroplating methods or apparatus H05K3/241
• CPC Class Codes: H05K 3/243 characterised by selective plating, e.g. for finish plating of pads selective plating for making the circuit pattern H05K3/108, H05K3/182
• CPC Class Codes: H05K 3/388 by the use of a metallic or inorganic thin film adhesion layer
• CPC Class Codes: H05K 3/423 characterised by electroplating method
• CPC Class Codes: H05K 3/4605 made from inorganic insulating material
• CPC Class Codes: H05K 3/4644 : by building the multilayer layer by layer, i.e. build-up multilayer circuits making via holes in the insulating layers H05K3/0011; special circuit boards as base or core whereon the multilayer is built H05K3/4602
• CPC Class Codes: H05K 3/4647 : by applying an insulating layer around previously made via studs
• CPC Class Codes: Y10T 29/49144 : by metal fusion
• CPC Class Codes: Y10T 29/49158 : with molding of insulated base

Abstract

A method for fabricating an interconnection package for a plurality of semiconductor chips which include the fabrication of a multi-layered glass-ceramic superstructure with a multi-layered distribution of conductors on a preformed multi-layered glass-ceramic base, by the repeatable steps of depositing a conductor pattern on the base and forming thereon a crystallizable glass dielectric layer which is then crystallized to a glass-ceramic prior to further additions of conductor patterns and crystallizable glass layers to form a monolithic compatible substrate all through. Semiconductor chips can be electrically connected to expose conductor patterns at the top surface of the resultant glass-ceramic package.

Claims

1. A method for fabricating a solid thermally compatible and integral glass-ceramic/metal electrical interconnection package adapted for bonding to semiconductor integrated circuit chips, comprising the steps of:

(a) providing a glass-ceramic substrate having a plurality of metallized conductive planes interconnected together in a predetermined pattern,

(b) forming a coating of a first metallized conductive pattern on the upper surface of said substrate in a predetermined pattern of interconnection to said planes,

(c) forming a plurality of vertical conductive studs on said surface and coating in a predetermined pattern of interconnection to said conductive planes and coating,

(d) forming a crystallizable glass layer on said surface having a temperature of crystallization below the melting point of said conductive coating and studs, wherein said substrate and said layer are selected from a glass-ceramic having either β

-spodumene or cordierite as the principle crystalline phase,

(e) heating said glass layer to the crystallization temperature thereof for sufficient time to crystallize said glass into a bubble-free glass-ceramic layer, said crystallization being effected without reflow of any underlying glass-ceramic layers or disruption of any lower levels of metallization and

(f) conditioning said glass-ceramic layer to expose at the top surface thereof said vertical conductive studs.

2. The method of claim 1 wherein said conductive planes comprise thick film metallurgy and said conductive coating comprises thin film metallurgy.

3. The method of claim 2 including the steps of electrically connecting at least one of said chips to said studs.

4. The method of claim 1 including the steps of electrically connecting at least one of said chips to said studs.

12. The method of claim 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 or 11 wherein said conductive planes and coating is selected from copper, gold or silver based metallurgy.

13. The method of claims 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 or 11 wherein said conductive planes and coating comprise copper based metallurgy.

5. A method for fabricating a solid all glass-ceramic/metal electrical interconnection package adapted for electrical connection to semiconductor integrated circuit chips, comprising the steps of:

(a) providing a glass-ceramic substrate having a plurality of metallized planes interconnected together in a predetermined pattern,

(b) forming a coating of a first metallized pattern on the upper surface of said substrate in a predetermined pattern of interconnection to said conductive planes,

(c) forming a plurality of conductive studs on said surface and coating in a predetermined pattern of interconnection to said conductive planes and coating,

(d) forming over said surface a crystallizable glass layer having a temperature of crystallization below the melting point of said conductive coating and studs, wherein said substrate and said layer are selected from glass-ceramics having either β

-spodumene or cordierite as the principle crystalline phase,

(e) heating said glass layer to the crystallization temperature thereof for sufficient time to crystallize said glass layer into a bubble-free glass-ceramic layer, said crystallization being effected without reflow of any underlying glass-ceramic layers or disruption of any lower levels of metallization,

(f) conditioning said glass-ceramic layer to expose at the top surface thereof said studs,

(g) forming on the exposed surface of the glass-ceramic layer an additional coating of a metallized pattern in a predetermined pattern of interconnection to underlying conductive planes, patterns and studs,

(h) forming a plurality of additional conductive studs on the said exposed glass-ceramic surface in a predetermined pattern of interconnection to underlying conductive planes, pattern and studs,

(i) forming over the underlying glass-ceramic layer an additional layer of said crystallizable glass having a temperature of crystallization below the melting point of the underlying conductive coatings and studs,

(j) heating said additional layer of glass to the crystallization temperature thereof for sufficient time to crystallize the glass layer into an additional bubble-free glass-ceramic layer, said crystallization being effected without reflow of any underlying glass-ceramic layers or disruption of any lower levels of metallization, and

(k) conditioning said additional glass-ceramic layer to expose at the top surface thereof the immediate underlying studs.

6. The method of claim 5 wherein said conductive planes comprise thick film metallurgy and said conductive coatings comprise thin film metallurgy.

7. The method of claim 6 including the steps of electrically connecting at least one of said chips to said studs.

8. The method of claim 5 including repeating Steps g to k thereof to obtain a desired number of levels of said conductive patterns.

9. The method of claim 8 wherein said conductive planes comprise thick film metallurgy and said conductive coatings comprise thin film metallurgy.

10. The method of claim 8 including the steps of electrically connecting at least one of said chips to said studs.

11. The method of claim 5 including the steps of electrically connecting at least one of said chips to said studs.