VMOS Floating gate memory device

• US 4,222,062 A
• Filed: 05/04/1976
• Issued: 09/09/1980
• Est. Priority Date: 05/04/1976
• Status: Expired due to Term

• Current Assignee: American Microsystems Limited Incorporated (ON Semiconductor Corporation)
• Original Assignee: American Microsystems Limited Incorporated (ON Semiconductor Corporation)
• Inventors: Rodgers, Thurman J., Trotter, James D.
• Primary Examiner(s): Larkins, William D.
• Application Number:
  US05/683,185
• Time in Patent Office: 1,589 Days
• Field of Search: 357/23, 357/41, 357/54, 357/60, 357/59, 357/45, 365/184, 365/185
• US Class Current: 257/316
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 17/12 using field-effect devices
• CPC Class Codes: H01L 27/0733 in combination with capacitors only
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7886 Hot carrier produced by avalanche breakdown of a PN junction, e.g. FAMOS
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 41/23 with source and drain on different levels, e.g. with sloping channels
• CPC Class Codes: Y10S 148/168 V-Grooves
• CPC Class Codes: Y10S 257/927 Different doping levels in different parts of PN junction to produce shaped depletion layer

Abstract

A semiconductor programmable read only memory device (PROM) utilizes an array of memory cells each having an area basically defined by the intersection of a bit line and a word address line. On a substrate of one conductivity type is an upper layer of material of the opposite conductivity within which are diffused bit lines of the same conductivity material as the substrate. The crossing address lines are conductive material formed on an insulating layer that covers the diffused bit lines and the upper layer. Each cell is a single transistor element in the form of a V-type MOSFET which achieves the normal AND function (Data-Word Address) using a capacitance coupled version of threshold logic. Each MOSFET is formed by a V-shaped recess at the intersection of each bit line and address line that extends through the diffused bit line, (which serves as the transistor drain) and into the substrate (which serves as the source and ground plane of the device). A similarly V-shaped floating gate is isolated below and above the crossing bit and address lines by thin oxide layers. Data is written into the cell when hot electrons are injected into the gate oxide near the drain junction and attracted to the floating gate which has been charged positive by capacitance coupling from the word line. The hot electrons are generated from the channel current via impact ionization at the pinched-off drain junction.

Claims

1. A semiconductor programmable read only memory device comprising:

a semiconductor substrate having a preselected conductivity;

a layer of semiconductor material having the opposite conductivity from and extending across said substrate;

a series of elongated, spaced apart, diffused regions in said layer of semiconductor material having the same conductivity as said substrate and forming buried bit lines;

a layer of insulating material on said diffused bit line regions and said layer of semiconductor material;

a series of elongated, spaced apart conductive regions forming word lines on said layer of insulating material and oriented transversely to said bit lines;

a series of recesses spaced apart along each of said bit lines at locations where said word lines cross over said bit lines, each said recess extending through a said bit line and into said substrate and having a "V" shaped cross section;

a floating gate of conductive material within each said recess and having a similar "V" shaped cross section, each said gate extending downwardly from a drain region formed by a said diffused bit line to a common source region formed by said substrate;

a first thin dielectric layer between each said floating gate and covering the side walls of its said recess;

a second thin dielectric layer between each said floating gate and a said word line directly above it; and

surface bit lines of conductive material located on the surface of said device directly above said buried bit lines and connected thereto at preselected locations by contacts extending downwardly through said insulating layer.

2. The semiconductor memory device according to claim 1 wherein said semiconductor substrate is of >

100<

plane silicon material having an N+ type conductivity, said layer of semiconductor material on said substrate is an epitaxial layer of lightly doped P type conductivity material and said buried bit lines also have an N+ type conductivity.