Display stabilization circuit

• US 4,224,569 A
• Filed: 07/19/1978
• Issued: 09/23/1980
• Est. Priority Date: 07/19/1978
• Status: Expired due to Term

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Campbell, Eugene H.
• Primary Examiner(s): Tokar, Michael J.
• Application Number:
  US05/920,222
• Time in Patent Office: 797 Days
• Field of Search: 324/78 R, 324/78 D, 324/77 A, 324/99 D, 235/92 EA
• US Class Current: 324/76.63
• CPC Class Codes: G01R 13/02 for displaying measured electric variables in digital form
• CPC Class Codes: G01R 15/00 Details of measuring arrangements of the types provided for in groups G01R17/00 - G01R29/00, G01R33/00 - G01R33/26 or G01R35/00

Abstract

A stabilized display for electronic instruments that make voltage measurements, frequency measurements, and the like is disclosed. This stabilized display includes a counter, a register, a comparator, and control logic. The counter generates counts, during spaced apart time intervals, that are representative of measurements made by the instrument. Selected ones of these counts are transferred to the register in response to a LATCH signal, where they are displayed. The comparator connects to the counter and the register. It generates output signals indicating whether or not the contents of the counter and register are equal. These output signals are received by the control logic, which generates the LATCH signal in response to a predetermined sequence of non-equality indications from the comparator.

Claims

1. An electronic instrument having a stabilized display, said instrument comprising:

counter means for counting clocking signals during spaced apart time intervals to generate a count in each of said intervals representative of a measurement made by said instrument;

register means coupled to said counter means for storing selected ones of said counts in response to a LATCH signal;

display means coupled to said register means for visually displaying characters representative of the count held in said register means;

comparator means coupled to said counter means and to said register means for generating an output signal between each of said time intervals indicating whether or not the contents of said counter means and said register means are equal; and

control means for generating said LATCH signal in response to a predetermined sequence of non-equality indications from said comparator means, and for generating said LATCH signal for each successive non-equality indication from said comparator means after said predetermined sequence.

2. An instrument according to claim 1, wherein said control means includes means for holding a predetermined number of the most recently generated output signals, and means for generating said LATCH signal in response to all of said held output signals indicating a miscompare.

3. An instrument according to claim 2, wherein said means for holding said output signals is a shift register.

4. An instrument according to claim 2, wherein said predetermined number is between 2 and 5 inclusive.

5. An instrument according to claim 1, wherein said control means includes means for holding a predetermined number of the most recently generated output signals, and means for generating said LATCH signal in response to at least 50% of said held output signals indicating a miscompare.

6. An instrument according to claim 5, wherein said means for holding said output signals is a shift register.

7. An instrument according to claim 5, wherein said predetermined number is between 2 and 5 inclusive.

8. An instrument according to claim 1, wherein said counter means generates a count in each of said time intervals representative of a measured voltage.

9. An instrument according to claim 1, wherein said counter means generates a count in each of said time intervals representative of a measured frequency.