Advanced data link controller

• US 4,225,919 A
• Filed: 06/30/1978
• Issued: 09/30/1980
• Est. Priority Date: 06/30/1978
• Status: Expired due to Term

• Current Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Hepworth, Edward C., Kyu, Shikun
• Primary Examiner(s): Springborn, Harvey E.
• Application Number:
  US05/921,012
• Time in Patent Office: 823 Days
• Field of Search: 179/15 AF, 179/15 AL, 364/200 MS File, 364/900 MS File
• US Class Current: 710/305
• CPC Class Codes: G06F 13/32 using combination of interrupt and burst mode transfer
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: H04L 12/5692 Selection among different networks

Abstract

A bit-oriented data link controller provides the interface between a microcomputer or terminal and a data communications link. The data link controller is capable of accommodating the three most commonly available bit-oriented data link control protocols, namely Synchronous Data Link Control SDLC, High Level Data Link Control HDLC, and Advanced Data Communications Control Procedure ADCCP. The data link controller provides the data communications interface for both primary and secondary stations in stand-alone, polling, and loop configurations.

Claims

1. In a data link controller for controlling data communications between a bidirectional data bus and a communications link transmitting and receiving data in serial form, said data link controller comprising a transmitter, a receiver, and a status register, the improvement wherein said status register comprises a plurality of individual bit locations each of which may be concurrently set to a predetermined logic state by control logic in response to one of a first set of operating conditions within said data link controller and which locations may be subsequently read by a data processing system located externally to said data link controller and coupled to said bidirectional data bus, said individual bit locations being arranged in a first prioritized pattern, said data processing system controlling the operation of said data link controller in response to the contents of said status register bit locations in accordance with said first prioritized pattern.

2. The data link controller recited in claim 1 further comprising an additional status register, said additional status register comprising a plurality of individual bit locations each of which may be concurrently set to said predetermined logic state by said control logic in response to one of a second set of operating conditions within said data link controller and which locations may be subsequently read by said data processing system, said individual bit locations of said additional status register also being arranged in a second prioritized pattern, said data processing system controlling the operation of said data link controller in response to the contents of the status register bit locations of both of said status registers in accordance with a prioritization arrangement which represents a combination of said first and second prioritized patterns.

3. The data link controller recited in claim 2 wherein one of said individual bit locations of said status register may be set in response to one of said first set of operating conditions to indicate that said additional status register should be read by said data processing system, and said one bit location may be cleared in response to another of said first set of operating conditions to indicate that said additional status register need not be read by said data processing system.

4. The data link controller recited in claim 2 and further comprising:

a control register coupled to said bidirectional data bus and loadable with a plurality of control bits by said data processing system, one of said control bits having first and second logic states, said control logic being responsive to the contents of said control register,

wherein said control logic inhibits the setting of all status register bit locations of said status register and of said additional status register having a priority less than that of any particular bit location which has been set in said status register or in said additional status register, respectively, in response to said first logic state of said one control bit, and

wherein said control logic does not inhibit the setting of any status register bit locations of said status register or of said additional status register, in response to said second logic state of said one control bit.

5. The data link controller recited in claim 1 wherein said transmitter comprises a plurality of registers each having N stages for storing information, each stage storing a single bit, N being a positive integer, wherein said data communications occur in serial form as a succession of N-bit frames, and wherein different ones of said status register bit locations may be loaded with ones of said first set of operating conditions providing status information regarding two different frames, portions of which are residing simultaneously within said plurality of N-stage registers.

6. The data link controller recited in claim 1 wherein said receiver comprises a plurality of registers each having N stages for storing information, each stage storing a single bit, N being a positive integer, wherein said data communications occur in serial form as a succession of N-bit frames, and wherein different ones of said status register bit locations may be loaded with ones of said first set of operating conditions providing status information regarding two different frames, portions of which are residing simultaneously within said plurality of N-stage registers.

7. The data link controller recited in claim 1 and further comprising:

a control register coupled to said bidirectional data bus and loadable with a plurality of control bits by said data processing system, one of said control bits having first and second logic states, said control logic being responsive to the contents of said control register, and

wherein said control logic inhibits the setting of all status register bit locations of said status register having a priority less than that of any particular bit location which has been set, in response to said first logic state of said one control bit, and

wherein said control logic does not inhibit the setting of any status register bit locations of said status register, in response to said second logic state of said one control bit.