Power control circuit and a switching mode power supply employing this circuit

• US 4,228,493 A
• Filed: 12/21/1978
• Issued: 10/14/1980
• Est. Priority Date: 12/29/1977
• Status: Expired due to Term

• Current Assignee: Thomson-CSF (Thales SA)
• Original Assignee: Thomson-CSF (Thales SA)
• Inventors: Geiger, Erich, de Sartre, Jean
• Primary Examiner(s): Beha, Jr., William H.
• Application Number:
  US05/972,058
• Time in Patent Office: 663 Days
• Field of Search: 363/20, 363/21, 363/56, 363/80, 363/97, 363/131, 363/147, 323/17
• US Class Current: 363/56.1
• CPC Class Codes: H02M 1/0032 Control circuits allowing low power mode operation, e.g. in standby mode
• CPC Class Codes: H02M 3/335 using semiconductor devices only
• CPC Class Codes: H02M 3/33523 with galvanic isolation between input and output of both the power stage and the feedback loop
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

A power control circuit for controlling the base current to a switching transistor connected in series with a primary winding of a switching transformer in which a logic circuit controls first and second amplifiers which respectively supply base current to and absorb base current from the switching transistor. The logic circuit blocks base current flow whenever the current flow through the transistor or a secondary winding of the transformer exceeds predetermined values in accordance with timing pulses.

Claims

1. A power control circuit for controlling the base current to a switching transistor connected in series with a primary winding of a switching transformer comprising:

first means for detecting the current flow through said transistor and producing a first signal when said current flow exceeds a first predetermined value;

second means for detecting the current flow through a secondary winding of said transformer and producing a second signal when current flow through said second winding exceeds a second predetermined value;

means for generating a sawtooth waveform and comparing said waveform to a reference voltage to produce a sequence of timing pulses;

first amplifier means for supplying base current to said switching transistor;

second amplifier means for absorbing base current from said switching transistor, said base current being cyclically supplied to and absorbed from said transistor;

logic means connected to said first and second detecting means, said generating and comparing means and said first and second amplifier means for controlling supplying of base current to and absorbing current from said switching transistor in accordance with said pulses and said first and second signals.

2. A circuit as in claim 1, further including third means for detecting the supply voltage and producing a third signal when said supply voltage is less than a given value, said logic means controlling also in accordance with said third signal to prevent supplying current when said third signal is being produced.

3. A circuit as in claim 1 or 2 wherein said logic means blocks base current whenever one of said signals is produced.

4. A circuit as in claim 1 or 2 further including means for comparing the saturation voltage of said transistor with a reference voltage and producing a signal to cause said logic means to prevent supplying current when said saturation voltage is greater than said reference voltage.

5. A circuit as in claim 1, wherein said logic means includes a plurality of logic gates.

6. A circuit as in claim 1 or 2 wherein said logic means prevents supplying said base current and absorbing said base current when one of said signals is produced.

7. A circuit as in claim 1, wherein said generating and comparing means includes means for ensuring that each pulse has a duration at least equal to the discharge time of a capacitor through said switching transistor to protect said transistor.

8. A circuit as in claim 1, including comparator means connected to said voltage means for comparing the saturation voltage of said transistor with a reference voltage and a time delay circuit connected to said comparator means and logic means for preventing simultaneous conduction of said first and second amplifier means.

9. A circuit as in claim 1, wherein said means are all integrated in a monolithic circuit on a single semi-conductor crystal.