Memory with redundant rows and columns
First Claim
1. A semiconductor memory (10) comprising a semiconductor chip in which memory cells are arranged in vertical and horizontal lines each with its own decoder and in which some of the lines form the standard memory array (12) and some of the lines (13, 14) are initially spares to be substituted for lines which include defective cells characterized in that each of the decoders (20) associated with the standard lines includes means (21) for disconnecting the associated line from the standard memory array and in which each of the decoders (30) associated with the spare lines includes means (41) for providing any such decoder with the address of a decoder associated with a disconnected line, thereby effectively substituting its associated line in the standard array.
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Abstract
A memory is provided with standard rows and columns and spare rows and columns for substitution for standard rows and columns found to have defective cells. Each of the decoders associated with a standard row and/or column includes provision for being disconnected if found to be associated with a defective row or column. Each of the decoders associated with a spare row and/or column is designed normally to be deselected for any address but to be able to assume the address of any disconnected row or column. Disconnection of the standard decoders and substitution of the spare decoders are made possible by appropriate inclusion of fusible links which can be selectively opened by laser irradiation.
69 Citations
6 Claims
- 1. A semiconductor memory (10) comprising a semiconductor chip in which memory cells are arranged in vertical and horizontal lines each with its own decoder and in which some of the lines form the standard memory array (12) and some of the lines (13, 14) are initially spares to be substituted for lines which include defective cells characterized in that each of the decoders (20) associated with the standard lines includes means (21) for disconnecting the associated line from the standard memory array and in which each of the decoders (30) associated with the spare lines includes means (41) for providing any such decoder with the address of a decoder associated with a disconnected line, thereby effectively substituting its associated line in the standard array.
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5. A process for making a semiconductive memory which includes initially providing on a single chip a plurality of storage cells arranged in vertical and horizontal lines each with its own decoder, some of which form the standard array and some of which form spares and later involves substituting for lines having defective storage cells in the standard array spare lines free of defective storage cells characterized in that
each spare line is provided with its spare decoder which normally keeps such line effectively deselected, after testing the lines of the standard array to ascertain the address of defective cells, the decoders associated with the lines including any such defective cells are disabled to disconnect its line from the standard array, and the address of any such disconnected decoder is given to a spare decoder whereby the line associated with such decoder becomes effectively selected as part of the standard array.
Specification
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- Resources
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Current AssigneeBell Telephone Laboratories, Inc. (Nokia Corporation)
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Original AssigneeBell Telephone Laboratories, Inc. (Nokia Corporation)
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InventorsProcyk, Frank J., Cenker, Ronald P.
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Primary Examiner(s)Fears, Terrell W.
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Application NumberUS06/010,739Time in Patent Office613 DaysField of Search365/200, 365/210, 307/238, 307/274US Class Current365/200CPC Class CodesG11C 29/781 combined in a redundant dec...
