Time division digital communication system

• US 4,228,536 A
• Filed: 05/29/1979
• Issued: 10/14/1980
• Est. Priority Date: 05/29/1979
• Status: Expired due to Term

• Current Assignee: Redcom Laboratories, Inc.
• Original Assignee: Redcom Laboratories, Inc.
• Inventors: Breidenstein, Charles J., Gueldenpfennig, Klaus
• Primary Examiner(s): Olms, Douglas W.
• Application Number:
  US06/042,742
• Time in Patent Office: 504 Days
• Field of Search: 179/15 AT, 179/15 AQ, 179/15 BS, 370/66, 370/68, 370/100
• US Class Current: 370/376
• CPC Class Codes: H04Q 11/0407 using a stored programme control
• CPC Class Codes: H04Q 2213/13103 Memory
• CPC Class Codes: H04Q 2213/13106 Microprocessor, CPU
• CPC Class Codes: H04Q 2213/13292 Time division multiplexing, TDM
• CPC Class Codes: H04Q 2213/13299 Bus
• CPC Class Codes: H04Q 2213/1332 Logic circuits
• CPC Class Codes: H04Q 2213/13322 Integrated circuits
• CPC Class Codes: H04Q 2213/13393 Time slot switching, T-stage, time slot interchanging, TSI

Abstract

A time division digital communication system which does not require a common control unit for accomplishing interconnections, having a plurality of modular switching units. The switching units are identical and each unit has its own port circuits to which subscriber lines and/or trunks may be connected, service circuits, a time slot interchange and a microprocessor control and timing unit. The switching units are in direct communication via separate send highways, one for the port circuits and the other for the service circuits of each switching unit. The microprocessors of each switching unit are also in direct communication by way of control lines. The inter-switching unit send highways are connected to separate channels or groups of memory locations in the time slot interchanges of each of the switching units. By selective listening to receive highways connected to the output of the time slot interchanges, any port or service circuit, whether in its own switching unit or any of the other switching units, can be interconnected. These interconnections are made under microprocessor control on the basis of events such as off-hook conditions and dialed digits from the ports, rather than by central or call processing. The switching of calls is non-blocking, as any port can be connected to any one or more of the other ports or service circuits at all times.

Claims

1. A time division switching system for providing two-way communication between a plurality of circuits arranged in a plurality of groups, said system comprising

a time slot interchange having a plurality of groups of memory sections each corresponding to at least one of said circuit groups, said memory sections each having a plurality of memory locations each corresponding to a different one of the sequential time slots of the plurality of circuits in its corresponding circuit group,

a plurality of send highways between said corresponding circuit group and memory section group,

a plurality of receive highways each for a separate one of said circuit groups,

means for connecting each of said receive highways selectively to any of said memory sections,

timing and control means for transmitting data signals simultaneously in each of said time slots along said send highways from all of said circuit groups to said memory sections for storage in different ones of said plurality of locations and for transferring data signals stored in said locations selectively to different ones of said receive highways to the circuit group therefor through said connecting means in different ones of said time slots to provide bidirectional communications among any of said circuits in the same circuit group and in different ones of said circuit groups.

2. The invention as set forth in claim 1 further comprising at least a second plurality of circuits arranged in a plurality of second groups, which share sequential time slots occurring synchronously with the time slots for said first plurality of circuits, a second time slot interchange having a plurality of memory sections each corresponding to at least one of said second circuit groups and to at least one of the first circuit groups of the first plurality of circuits, said second memory sections also each having a plurality of memory locations each corresponding to a different one of said sequential time slots, the first time slot interchange also having memory sections corresponding to at least one of said second circuit groups, a second plurality of send highways between corresponding second circuit groups and memory sections of said second time slot interchange, said second send highways also being connected to said memory sections in said first time slot interchange corresponding thereto, said first send highways also being connected to the memory sections of said second time slot interchange corresponding thereto, a second plurality of receive highways each for a separate one of said second circuit groups, second means for connecting each of said second receive highways to any of said memory sections of said second time slot interchange, said means for selectively connecting said first mentioned receive highways to said memory sections of said first time slot interchange also being for connecting said first mentioned receive highways to said memory sections of said first time slot interchange corresponding to said second circuit groups, second timing and control means for transmitting data signals along said send highways to said memory sections of said second interchange for storage in different ones of said plurality of locations therein and for transferring data signals stored in said locations therein to different ones of said second receive highways through said second connecting means, and said first and second control and timing means having direct connections for control and timing signals therebetween.

3. The invention as set forth in claim 1 wherein said plurality of groups of circuits comprise a first group of circuits and a second group of circuits for sending and receiving digital signals, said plurality of groups of memory sections comprise first and second memory section groups, said first memory section group having first and second memory sections corresponding to said first and second group of circuits, respectively, said second memory section group having third and fourth memory sections corresponding to said first and second group of circuits, respectively, said plurality of send highways comprise a first send highway between said first circuit group and said first and third memory sections, a second send highway between said second circuit group and said second and third memory sections, said plurality of receive highways comprise a first receive highway for said first circuit group and a second receive highway for said second circuit group, said connecting means comprise first and second switch means for connecting said first and second memory sections selectively to said first receive highway and said third and fourth memory sections selectively to said second receive highway.

4. The invention as set forth in claim 3 wherein said first circuit group consists of a plurality of port circuits for telephone lines not exceeding in number the number of said sequential time slots in a sequential frame of said slots and said plurality of service circuits in number not exceeding said number of said time slots.

5. The invention as set forth in claim 1 wherein said timing and control means for sequentially providing first digital control signals representing the locations in said group of memory sections containing data from the ones of said circuits which are sending and second digital control signals representing the ones of said circuits which are receiving, and means responsive to said second control signals for reading said data signals stored in said groups of memory sections in the locations represented by said first signals onto said receive highways in time slots allocated to said receiving circuits.

6. The invention as set forth in claim 5 wherein said means for reading onto said receive highways comprises a random access memory having storage for said first control signals in a plurality of locations equal in number to the number of said plurality of locations in each of said groups of memory sections, register means for storing successive ones of said first control signals, means operated by said second control signals for transferring said first control signals successively from selected locations in said random access memory to said register means, and said register means being connected to said memory groups and to said connecting means for reading out said memory group locations for reading out said locations onto said receive highway.

7. The invention as set forth in claim 6 wherein said reading out means comprises a counter operative synchronously with the occurrence of said time slots, for sequentially providing first signals representing different ones of said random access memory locations, means for applying said first data signals to said random access memory locations represented by said counter signals, means responsive to second signals from said counter for timing the transfer of said first control signals to said register, said counter also providing third signals for transferring said data signals from said send highways into said memory section locations.

8. The invention as set forth in claim 7 further comprising means for generating fourth signals from said counter and applying said fourth signals to said circuits for successively enabling said circuits in each of said groups to transmit said data signals onto said second highways and receive said signals from said receive highways.

9. The invention as set forth in claim 8 wherein said fourth signal generating means comprises means for converting a plurality of the outputs of said counter into a multi-bit signal in accordance with a Gray code, said Gray code signal being said fourth signal.

10. The invention as set forth in claim 9 wherein said converting means comprises means for delaying said fourth signal the period of one time slot which comprises an adder connected to said counter for adding an integer to the number represented by the outputs of said counter, a Gray code converter, and applying a plurality of higher order bits represented by the outputs of said adder to said converter to provide said Gray code signal.

11. A TDM telecommunications system for providing two-way communications between a plurality of lines, said system comprising a plurality of switching units each serving a separate group of said lines, each of said units having port means interfacing with said lines for receiving and transmitting digital signals, time slot interchange means, and processor means, a send highway and a receive highway, said time slot interchange means, processor means and port means interfacing with each other to provide time division multiplexed receiving connections for digital signals through said time slot interchange means and receive highway, and time division multiplexed transmitting connections along said send highways to said time slot interchange means, and said switching units being in direct communication with each other via control lines interconnecting the processors thereof and said send highways interconnecting the time slot interchanges thereof.

12. The invention as set forth in claim 11 wherein each of said switching units further comprises a plurality of service circuits, a service send highway and a service receive highway, said service circuits having means for transmitting and receiving digital signals, said time slot interchange means, processor means and service circuit means interfacing with each other to provide time division multiplexed receiving connections for digital signals from said port means and service circuits in every one of said plurality of switching units through said service receive highway and to provide time division multiplexed transmitting connections along said service send highway to said time slot interchange means, and said switching units also being in direct communication with each other via said service send highways interconnecting the time slot interchanges thereof.

13. The invention as set forth in claim 12 wherein each of said time slot interchanges of each of said units has memory means with a separate group of digital signal storage locations for each of said port means send highways, and said service send highways, timing means for reading said digital signals from said port and service send highways in synchronism into said locations in its respective one of said groups of locations in said memory means.

14. The invention as set forth in claim 13 wherein said memory means comprises a pair of memories each having a pair of said groups of locations with one of said pair of groups providing storage for the digital signals from said port send highways and the other of said pair of groups providing storage for the digital signals from said service send highways, one of said pairs of groups being connected to said service receive highway of said unit and the other of said pair of groups being connected to said port receive highway of said unit.

15. The invention as set forth in claim 11 wherein said time slot interchange has a memory means providing a separate group of locations for each send highway from each switching unit, and timing means for writing said multiplexed digital signals from each said send highways in corresponding time slots simultaneously into each said groups of locations.

16. The invention as set forth in claim 15 wherein said processor means includes timing signal generating means, and said control lines include lines carrying timing signals generated by said timing signal generating means in one of said units to all of said units such that all of said units are operated synchronously in response to said timing signals.

17. The invention as set forth in claim 11 wherein said control lines include identification lines having means for providing different identification code outputs at a plurality of different positions therealong, said units being connected to said identification lines each at a different one of said positions, and means in the processor means of each of said units for deriving said different identification code outputs depending upon the one of said positions to which each said unit is connected.

18. The invention as set forth in claim 17 wherein said connections are provided at a plurality of connectors spaced successively along said identification lines, said connectors having a plurality of terminals at least equal in number to the number of switching units in said plurality of units, said lines being connected in staggered relationship to said terminals with one of said lines being connected to terminals in all of said connectors which are successively offset, the next of said lines connected to terminals in one less than all of said connectors which are successively offset from each other and from the terminals to which said one line is connected, and so forth, means for connecting a like positioned one of said terminals on each of said connectors to a reference potential, and said identification code deriving means being connected to the terminals of said connectors other than said one of said terminals.

19. The invention as set forth in claim 17 wherein said control lines also include a link line for carrying control data signals, a line for carrying timing signals and a line for carrying signals indicating that said link line is busy, means in each said processor means responsive to the identification code thereof for successively providing access to said link line for transmitting said control data signal from said processor means thereon in the absence of a busy condition signal being carried on said link busy line.

20. The invention as set forth in claim 19 wherein said means for successively providing access to said link line for transmitting control data signals comprises a counter for counting said timing signal for providing a code which changes successively, means responsive to said identification code and said counter code for providing an output in a different one of a plurality of successive periods of time for enabling access to be had to said link line, and means responsive to a request for access to said lines and said link busy line condition for providing access to said line upon occurrence of said output.