Programmable memory cell having semiconductor diodes

• US 4,229,757 A
• Filed: 08/31/1978
• Issued: 10/21/1980
• Est. Priority Date: 09/30/1977
• Status: Expired due to Term

• Current Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Original Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Inventors: Moussie, Michel
• Primary Examiner(s): Larkins, William D.
• Application Number:
  US05/938,470
• Time in Patent Office: 782 Days
• Field of Search: 357/45, 357/51, 357/59, 357/4, 357/68, 357/71, 307/238, 365/96, 365/103, 365/105
• US Class Current: 257/50
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: H01L 23/5252 comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/1021 including diodes only
• CPC Class Codes: H01L 29/04 characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes characterised by physical imperfections H01L29/30
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: Y10S 148/055 Fuse
• CPC Class Codes: Y10S 257/926 Elongated lead extending axially through another elongated lead

Abstract

Integrated electrically programmable read only memory cell having at least two back-to-back diodes.

A first diode is formed by a planar junction (7) between two superimposed regions (2, 6), the second diode is programmable and is formed by a lateral junction (11) between two coplanar zones (9, 10) of a thin semi-conductor layer isolated from the body by an insulating layer (8) having a contact aperture (18).

Claims

1. An integrated electrically programmable read only memory cell having at least a first and a second semiconductor diode in back-to-back arrangement, wherein

the first diode is a planar p-n junction formed between two superimposed regions of which at least one region extends on the upper part of a semiconductor body and the second diode is a lateral p-n junction formed between two co-planar zones of a thin layer of a semiconductor material extending locally on an insulating layer covering the said body;

a window in the said insulating layer ensuring a contact between the said layer and the said body at the site of the first diode, and

the area of the junction of the second diode being substantially smaller than that of the first.

2. A cell as claimed in claim 1, wherein said upper part of the body is a monocrystalline silicon and said thin layer is of polycrystalline silicon.

3. A cell as claimed in claims 1 or 2 wherein the section of the lateral junction between the two co-planar zones is smaller than one-tenth of the section of the planar junction between the two superimposed regions.

4. A cell as claimed in claims 1 or 2 wherein the outline of said thin layer presents a narrowing at the location of the junction between the two zones.

5. A cell as claimed in claims 1 or 2, wherein said zones of the thin layer are situated between two layers of insulating and passivating material, at least in the vicinity of the junction between said zones.

6. A cell as claimed in claims 1 or 2, wherein the region connected via the window in the insulating layer to one of the zones of the second diode is a planar region diffused in an upper layer of the body, said upper layer constituting the other region of said two superimposed regions of the first diode.

7. A cell as claimed in claims 1 or 2, wherein the region connected via a window in the insulating layer to one of the zones of the second diode is a portion of a first epitaxial layer covering a portion of a second epitaxial layer constituting the other region of the first diode.

8. A cell as claimed in claims 1 or 2, wherein the first diode is constituted by a junction formed between one of the two zones of the second lateral junction diode and an immediately underlying surface region of the substrate which surface region is of a conductivity type opposite to that of said one of the two zones of the second diode.

9. An integrated electrically programmable read only memory having a monocrystalline silicon body and having a plurality of cells as claimed in claim 1 or 2, in an XY-arrangement, wherein the lateral junction diodes of some but not all of the plurality of cells are electrically shorted.