Binary to ternary converter

• US 4,231,023 A
• Filed: 03/12/1979
• Issued: 10/28/1980
• Est. Priority Date: 03/12/1979
• Status: Expired due to Term

• Current Assignee: Singer Company (SVP Holdings Ltd.)
• Original Assignee: Singer Company (SVP Holdings Ltd.)
• Inventors: Warner, Richard C.
• Primary Examiner(s): Miller, Charles D.
• Application Number:
  US06/019,991
• Time in Patent Office: 596 Days
• Field of Search: 340/347 DD, 325/38 A, 178/66, 178/67, 178/68, 375/17, 375/19, 375/20
• US Class Current: 341/57
• CPC Class Codes: H03M 7/06 the radix thereof being a positive integer different from two
• CPC Class Codes: H04L 25/4923 using ternary codes H04L25/4927 takes precedence

Abstract

A circuit for converting serial binary coded ternary information received on one line into ternary signals for transmission on two lines. The presence or absence of a pulse in a first interval is compared with the presence or absence of a pulse in the succeeding interval and a voltage representing one ternary condition is transmitted on one line if pulses are present, on another line, if pulses are absent, and no signal is transmitted if alternating pulses are received.

Claims

1. A circuit for translating ternary data being transmitted in serial binary code on one input line into ternary data coded for binary transmission on two output lines, the input data signalling a first ternary state by means of a signal alternating at an established rate for at least one cycle, a second ternary state by the presence of a signal at a first level for the period of at least one cycle, and a third ternary state by the presence of a signal at a second level for the period of at least one cycle, including

(a) first means for storing the present state of the input signal during each half cycle and providing said state as an output;

(b) first logic means having as inputs the output of said means for storing and said input signal and providing an output when both are at said first level;

(c) second logic means having as inputs the output of said means for storing and said input signal and providing an output when both are at said second level;

(d) second means for storing the state of the output of said first logic means and providing said state as an output;

(e) third means for storing the state of the output of said second logic means and providing said state as an output; and

(f) a clock developing a clock signal occurring each half cycle synchronously with said input signal, each of said first, second and third means for storing responsive to said clock signal to store the state at their respective inputs and provide said states at their outputs, whereby, when said input signal remains at said first level for two half cycles, an output will be provided from said second means, when said input signal is at said second level for two half cycles, said third means for storing will provide an output and when said signal alternates between said first and second levels over a cycle, neither of said second and third means for storing will provide an output.

2. The circuit of claim 1 wherein each of said means for storing comprise a D-type flip-flop.

3. The circuit of claim 2 wherein said first logic means comprise an AND gate and said second logic means a NOR gate.