Remote control system capable of transmitting the information with the aid of an infra red beam using PPM or an ultrasonic beam using PDM

• US 4,231,031 A
• Filed: 04/07/1978
• Issued: 10/28/1980
• Est. Priority Date: 02/09/1977
• Status: Expired due to Term

• Current Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Original Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Inventors: Douglas, Terence A., Crowther, Gerald O., Farmer, Howard M.
• Primary Examiner(s): Bookbinder, Marc E.
• Application Number:
  US05/894,245
• Time in Patent Office: 935 Days
• Field of Search: 325/390-394, 325/55, 325/58, 325/37, 325/141-143, 325/321, 250/199, 358/194, 343/225-228, 340/365 R, 340/365 S, 340/167 A, 307/261, 307/268, 307/291, 328/119, 328/164
• US Class Current: 340/12.16
• CPC Class Codes: G08C 19/28 using pulse code
• CPC Class Codes: H03J 9/04 using ultrasonic, sonic or infrasonic waves
• CPC Class Codes: H03J 9/06 using electromagnetic waves other than radio waves, e.g. light

Abstract

A remote control system for TV receiver control. The system uses infra-red transmission to trasmit an infra-red data pulse on each edge of a pulse duration signal comprising a coded pattern of binary 0 and 1 bits which are formed by pulses of respective different lengths. The original pulse duration signal can be reconstituted at a receiver by a bistable element which is responsive to the infra-red data pulses. Since the regenerated modulating waveform could be in anti-phase with the original modulating waveform, the sequence of data pulses is transmitted twice and an additional data pulse is transmitted between successive transmissions, so that one or the other of the two regenerated modulating waveforms must be in phase with the original modulating waveform.

Claims

1. A remote control system comprising a transmitter having an encoder and a receiver having a decoder, in which each of a plurality of remote control functions is represented by a message sequence comprising a plurality of binary bits of which a binary bit 0 and a binary bit 1 are distinguishable from each other by having, for the whole duration of a bit period, different time ratios of two different parameters, being respectively a high level and a low level portion of a bit period, forming a pulse duration signal comprising an edge each time the said signal is changing from one level to the other, said message sequence being repeated at least twice by said transmitter, wherein in order to be able to use the same encoder at the transmitter side and the same decoder at the receiver side both for ultrasonic and infra-red transmission of said binary bits, the encoder comprises means for converting, in the case of infra-red transmission, said pulse duration signal into a pulse position modulation signal whereby a data pulse is transmitted on each edge of said pulse duration signal, and wherein the decoder comprises means for reconstituting, in case of infra-red transmission, the received pulse position modulation signal into the original pulse duration signal and wherein the encoder further comprises an extra pulse generator for generating an additional pulse (EP) which is transmitted between alternate message sequences whereby each alternate message sequence is inverted when decoded by said decoder to ensure that, in the event of undesirable initial message sequence inversion in the decoder, a correct message sequence is received at least once.

2. A transmitter for a remote control system as claimed in claim 1, wherein said message sequence comprises a flow of binary coded words, the first word being an m-bit start word common to all the remote control functions, the second word being an n-bit message word peculiar to a selected control function, and the third and fourth words being complements of the start and message words.

3. A transmitter for a remote control system as claimed in claim 2, wherein the start word comprises at least one alternating sequence of three binary bits.

4. A transmitter for use in a system as claimed in claim 1, wherein said means for converting the pulse duration signal into a pulse position modulation signal comprises a first AND-Gate to a first input terminal of which the pulse duration signal is applied, a second AND-Gate to a first input terminal of which a switching signal is applied, a transmission mode terminal to which is applied an information signal determining whether infra-red or ultrasonic transmission should occur, said transmission mode terminal being connected to a second input terminal of said second AND-Gate and through an inverter to a second input terminal of said first AND-Gate, and an OR gate having two inputs respectively coupled to the two outputs of the two AND-Gates and an output terminal coupled to a transmitting device.

5. A transmitter as claimed in claim 4, further comprising function selection means, a message encoder which in response to operation of the function selection means provides an n-bit binary coded message word appropriate to the selected function, a parallel-to-serial output shift register, a data selector which enables the output shift register to be loaded with either a message word or a fixed m-bit binary coded start word, a data pulse generator, means for controlling the generator from the output of the output shift register, a true-complement selector and timing control means which, in response to continued operation of the function selection means continously shifts the output shift register and controls the data selector and the true-complement selector so that the generator transmits data pulses corresponding to the modulating waveform of successive binary bits which form a repeated message sequence.

6. A receiver for use in a system as claimed in any of the claims 1 to 3, wherein said means in the decoder for reconstituting the received pulse position modulation signal into the original pulse duration signal are a first AND-Gate (G16) to a first input terminal of which the received signal is applied, a divide-by-two circuit (DR5) to an input terminal of which also said received signal is applied, a second AND-Gate (G17) a first input terminal of which is connected to an output terminal of said divide-by-two circuit (DR5), an input terminal (IR/US'"'"'), to which is applied an information signal indicating whether infra-red or ultrasonic transmission takes place, connected to a second input terminal of said second AND-Gate (G17) and through an inverter (IV3) to a second input terminal of said first AND-Gate (G16), and wherein the two output terminals of said two AND-Gates (G16, G17) are connected to two input terminals of an OR-Gate (G18) from the output terminal of which the pulse duration signal is obtained.

7. A receiver as claimed in claim 6, which further comprises a bit detector adapted to detect binary bits corresponding to received data pulses, an interrupt detector responsive to an interruption in the detection of the immediately successive bits by the bit detector, a serial-to-parallel input shift register into which the detected bits are fed, a monitoring unit, said monitoring unit being adapted to recognize either a start word or a complement start word in the input shift register, being settable by an output from the interrupt detector to recognize a start word, being adapted to provide a first output signal in response to the recognition of a start word which has followed an output from the interrupt detector and which is followed by the detection of n-bits, and being adapted to provide a second output signal in response to the recognition of a start word followed by the detection of n-bits followed by the recognition of a complement start word followed by the detection of a further n-bits, an n-bit store into which the contents of the input shift register are transferred in response to said first output signal from the monitoring unit, a comparator adapted to compare the contents of the input shift register and the store, and a bistable circuit, said bistable circuit having an output arranged to enable or disable a remote control function corresponding to the contents of the store, said bistable circuit having a first input arranged to provide a disable output from the bistable circuit in response to an output from the interrupt detector, a second input to which said output signal from the monitoring unit is applied as a clock signal, and a third input connected to an output of the comparator such that the condition of the comparator is transferred by said clock signal to the output of the bistable circuit as a corresponding enable or disable output.

8. A receiver as claimed in claim 7, wherein the bit detector includes means adapted to derive from the received data pulses a waveform of short pulses corresponding to a first type of binary bit and long pulses corresponding to a second type of binary bits, and up/down counter which counts in response to pulses from a clock, said up/down counter being responsive to the beginning of a waveform pulse to commence counting up from a clear condition and being responsive to the end of a waveform pulse to commence counting down, and means responsive to the end of a waveform pulse to enable either a first type or a second type binary bit to be fed into the input shift register at the beginning of the next waveform pulse according to whether or not the counter has counted down to the clear condition before the beginning of the next waveform pulse.

9. A receiver as claimed in claim 8, wherein the monitoring unit includes a start word detector and a complement start word detector connected to the input shift register, a latching circuit, said latching circuit being set in response to an interruption in the detection of immediately successive bits by the bit detector or being set by the complement start word detector, and reset by the start word detector, a counter which divides by at least 2n+m, said counter being clocked by the input pulse waveform, stopped in response to an interruption in the detection of immediately successive bits by the bit detector, and cleared and enabled to count in response to a set output from the latching circuit and the detection of a start word, and a decoding circuit, which decoding circuit decodes a count of n in the counter to give said first output signal and which is inhibited by an enable output from the bistable circuit, which decoding circuit also decodes a count of n+m in the counter to give an output signal which is arranged to stop the counter unless a complement start word is simultaneously detected, and which decoding circuit also decodes a count of 2n+m in the counter to give said second output signal and which is inhibited if the latching circuit is not set.