×

Multi-level large scale complex integrated circuit having functional interconnected circuit routed to master patterns

  • US 4,234,888 A
  • Filed: 07/26/1973
  • Issued: 11/18/1980
  • Est. Priority Date: 07/26/1973
  • Status: Expired due to Term
First Claim
Patent Images

1. A multi-level complex integrated circuit of the type which defines a configuration of signal-connect portions, vias and integrated circuits which are the same in location for a plurality of wafers having the same functional circuit type, including:

  • a wafer having a plurality of cells in a nonstandard yield distribution of usable cells;

    a first level of means for defining dielectric insulation formed on said wafer and having means for defining vias formed through said insulation for exposing signal-connects of selected ones of said usable cells;

    a first level of metalization formed on said first level dielectric insulation means including electrical conductor means routed between and from said exposed signal connects of said usable cells to signal-connect portions for interconnecting at least one of said selected usable cells into at least one functional circuit, and for defining a routing of said signal-connects of said selected usable cells to locations of circuits corresponding to the configuration of signal-connect portions which is the same for the plurality of the wafers having the same functional circuit type, at least one of said signal-connect portions being positioned substantially directly above at least one of said signal-connects and at least one other of said signal-connect portions being positioned above and substantially laterally spaced from at least a corresponding one of said signal-connects;

    a second level of means for defining dielectric insulation formed on said electrical conductor means and having means for defining vias formed through said second level dielectric insulation means corresponding to a configuration of means for defining the vias which is the same for the plurality of the wafers having the same functional circuit type for having exposed said signal-connect portions of said electrical conductor means at the circuit locations; and

    at least a second level of metalization formed on said second level of dielectric insulation means including means for defining electrical interconnects routed between and from said exposed signal-connect portions at the circuit locations and corresponding to the configuration of integrated circuits which is the same for the plurality of the wafers having the same functional circuit type for having interconnected said selected usable cells into the functional circuit type.

View all claims
  • 0 Assignments
Timeline View
Assignment View
    ×
    ×