Multi-level large scale complex integrated circuit having functional interconnected circuit routed to master patterns

• US 4,234,888 A
• Filed: 07/26/1973
• Issued: 11/18/1980
• Est. Priority Date: 07/26/1973
• Status: Expired due to Term

• Current Assignee: Hughes Aircraft Company (Rtx Corporation)
• Original Assignee: Hughes Aircraft Company (Rtx Corporation)
• Inventors: Calhoun, Donald F., Bennett, Barry
• Primary Examiner(s): Smith, Jr., David
• Application Number:
  US05/382,993
• Time in Patent Office: 2,672 Days
• Field of Search: 29/574, 317/101 A, 357/40, 357/54, 357/45, 357/71
• US Class Current: 257/211
• CPC Class Codes: H01L 23/52 Arrangements for conducting electric current within the device in operation from one component to another , i.e. interconnections, e.g. wires, lead frames optical interconnections G02B6/00
• CPC Class Codes: H01L 23/535 including internal interconnections, e.g. cross-under constructions internal lead connections H01L23/481
• CPC Class Codes: H01L 27/118 Masterslice integrated circuits
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A complex integrated circuit comprising a wafer which has a plurality of cells each having signal-connect pads in a first layer of metalization on the wafer and which has an imperfect yield of usable cells. The circuit further includes a laminae of alternate layers of dielectric insulation and metalization formed on the wafer wherein: a first layer of insulation has vias formed therethrough to expose signal-connect pads of selected usable cells; a second layer of metalization has conductors formed therein which operably interconnect the exposed signal-connect pads of one or more groups of usable cells into individual functional circuits and, where needed, include pad relocation conductors which route the signal-connects of individual cells and the signal-connects of interconnected groups of cells to master pattern circuit locations; a second layer of insulation has vias formed therethrough which expose signal-connect portions at the master pattern circuit locations; and a third layer of metalization is formed into conductors that interconnect the signal-connects at master pattern locations into a functionally specified circuit type.

Claims

1. A multi-level complex integrated circuit of the type which defines a configuration of signal-connect portions, vias and integrated circuits which are the same in location for a plurality of wafers having the same functional circuit type, including:

a wafer having a plurality of cells in a nonstandard yield distribution of usable cells;

a first level of means for defining dielectric insulation formed on said wafer and having means for defining vias formed through said insulation for exposing signal-connects of selected ones of said usable cells;

a first level of metalization formed on said first level dielectric insulation means including electrical conductor means routed between and from said exposed signal connects of said usable cells to signal-connect portions for interconnecting at least one of said selected usable cells into at least one functional circuit, and for defining a routing of said signal-connects of said selected usable cells to locations of circuits corresponding to the configuration of signal-connect portions which is the same for the plurality of the wafers having the same functional circuit type, at least one of said signal-connect portions being positioned substantially directly above at least one of said signal-connects and at least one other of said signal-connect portions being positioned above and substantially laterally spaced from at least a corresponding one of said signal-connects;

a second level of means for defining dielectric insulation formed on said electrical conductor means and having means for defining vias formed through said second level dielectric insulation means corresponding to a configuration of means for defining the vias which is the same for the plurality of the wafers having the same functional circuit type for having exposed said signal-connect portions of said electrical conductor means at the circuit locations; and

at least a second level of metalization formed on said second level of dielectric insulation means including means for defining electrical interconnects routed between and from said exposed signal-connect portions at the circuit locations and corresponding to the configuration of integrated circuits which is the same for the plurality of the wafers having the same functional circuit type for having interconnected said selected usable cells into the functional circuit type.

2. The circuit of claim 1 in which said signal-connects include a pad dimension greater than the width of individual ones of said electrical conductor means.

3. The multi-level complex integrated circuit of claim 1 in which said electrical conductor means in said first level of metalization formed on said first level of dielectric insulation means includes cell interconnect conductors routed between said exposed signal-connects of at least two of said selected usable cells for functionally coupling said selected usable cells, said cell interconnect conductors being routed to the circuit locations.

4. The multi-level complex integrated circuit of claim 1 in which said electrical conductor means in said first level of metalization formed on said first level of dielectric insulation means includes signal-connect relocation conductors routed substantially laterally across the wafer from said corresponding one of said exposed signal-connects associated with said selected usable cells to said corresponding one of said signal-connect portions at the circuit locations.

5. The circuit means of claim 4 in which said signal-connect means further includes a pad dimension greater than the width of individual ones of said electrical conductor means.

6. The multi-level complex integrated circuit of claim 1 in which said electrical conductor means in said first level of metalization formed on said first level of dielectric insulation means includes cell interconnect conductors routed between said exposed signal-connects of individual groups of said selected usable cells for functionally coupling said selected usable cells together, and includes signal-connect relocation conductors routed substantially laterally across said wafer from said cell interconnect conductors to the circuit locations which are the same for the plurality of the wafers having the same functional circuit type for defining a routing of a portion of said selected usable cells including said corresponding one other of said signal-connect portions which are not vertically coincident with any of the circuit locations.

7. The multi-level complex integrated circuit of claim 6 in which said electrical conductor means includes signal-connect conductors routed substantially vertically from said exposed signal-connects of single ones of said usable cells vertically aligned with the circuit locations.

8. The multi-level complex integrated circuit of claim 1 in which said electrical conductor means in said first layer of metalization formed on said first level of dielectric insulation means is routed in a pattern corresponding to the yield distribution of usable cells of an individual wafer, and said electrical interconnect means in said second level of metalization are routed in the pattern common to all the wafers which have signal-connect portions at the circuit locations and which are interconnected into the functional circuit type.

9. A complex integrated circuit structure in a single body which defines a configuration at least of circuit locations and electrical routings that are the same in location for all other circuit structures capable of performing a particular electrical function, the structure comprising:

an array of cells of which some are usable and the remainder are nonusable, each of said cells having a plurality of signal-connects, said cell array having random positions of said usable and nonusable cells, said cell including a plurality of said usable cells selected from any of said usable cells irrespective of the random positions and being at least equal in number to the number of usable cells required to perform the electrical function;

said selected usable cells being interconnected for performing the electrical function by a plurality of interconnection layers including at least first and second interconnection layers of first interconnections and second interconnections respectively;

at least a first dielectric layer between said first interconnection layer and said signal-connects of said cells, said first dielectric layer having means therein for defining a plurality of first apertures, each of said first aperture means being aligned in registry with each of said signal-connects of said selected usable cells, each of said first interconnections extending through each of said first aperture means of said first dielectric layer and connected to each of said signal-connects of said selected usable cells, said first dielectric layer covering and otherwise electrically insulating said usable and nonusable cells and said signal-connects of said usable cells not selected from said cell array;

a second dielectric layer between said first interconnection layer and said second interconnection layer, said second dielectric layer having means therein for defining a plurality of second apertures, each of said second interconnections extending through each of said second aperture means of said second dielectric layer into connection with at least each of said first interconnections of said first interconnection layer, for interconnecting said second interconnection layer to said selected usable cells, and for interconnecting each of said second interconnections respectively to at least each of said signal-connects of at least one of said selected usable cells by at least one continuous substantially vertically extending interconnection path from said second interconnection layer through said first and second aperture means of said dielectric layers; and

said first interconnections terminating in locations of circuits defined by said second aperture means and corresponding to the configuration of the circuit locations which are the same for all the other circuit structures for performing the electrical function, and at least two of said selected usable cells interconnected to each other by means for defining the routings contained entirely within said first interconnection layer for coupling at least one of said second interconnections to said routing means, said routing means corresponding to the configuration of the electrical routings which is the same for all the other circuit structures for performing the electrical function.

10. The structure set forth in claim 9 in which said first interconnections of said first interconnection layer include conductors routed among said signal-connects of different ones of said selected usable cells, said conductors being routed to said locations of circuits, at least some of said signal-connects of said selected usable cells being substantially vertically aligned with said second aperture means of said second dielectric layer.

11. The structure set forth in claim 9 in which some of said first interconnections of said first interconnection layer are routed from corresponding ones of said first aperture means of said first dielectric layer to said locations of circuits which are laterally spaced on the single body from said corresponding ones of said first aperture means and aligned with corresponding ones of said second aperture means of said second dielectric layer.

12. The structure set forth in claim 9 in which said first interconnections of said first interconnection layer further includes a first group of conductors routed on said first dielectric layer between said signalconnects of individual groups of said selected usable cells including at least said two of said selected usable cells for forming a partial integration thereof into the electrical function, and a second group of conductors routed on said first dielectric layer from said first group of said conductors to said locations of circuits.

13. The structure set forth in claim 11 in which said first interconnections include conductors routed from said signal-connects of single ones of said selected usable cells to said locations of circuits.

14. The structure set forth in claim 9 in which said first interconnections are routed in a pattern corresponding to the yield distribution of said usable cells and in which said second interconnections are routed in a pattern which is fixed with respect to said signal-connects and located at said locations of circuits.

15. A plurality of integrated circuit members each capable of performing the same electrical function, and each comprising:

a plurality of functionally separate circuits on each of said circuit members in which some of said circuits are operable and the remainder are inoperable and in which the operable and the inoperable circuits are randomly positioned on each of said circuit members in a first level of metalization, each of said functionally separate circuits having means for defining a plurality of primary signal-connects associated therewith, said functionally separate operable circuits including a number of said operable circuits selected from any of said operable circuits irrespective of the positions of said operable circuits and at least being capable of performing the electrical function;

means for defining a plurality of secondary signal-connects at a second level of metalization otherwise electrically isolated from said functionally separate circuits and said primary signal-connects by means for defining electrical insulation having means therethrough for defining vias, said secondary signal-connect means being interconnected there-amongst for partially integrating said selected operable circuits into the electrical function and having locations identical among all of said circuit members, in which some of the identical locations are spaced substantially laterally from and others thereof are positioned substantially directly above said primary signal-connect means of said selected operable circuits; and

means for defining electrical conductors for coupling said secondary signal-connect means through said vias means to said primary signal-connect means and for at least partially integrating said selected operable circuits into the electrical function.

16. The improvement of claim 15 further comprising:

means on each of said integrated circuit members for defining a first level layer of said electrical conductor means coupled in the partial circuit integration to said primary signal-connect means of said selected operable circuits and routed over each of said integrated circuit members in otherwise electrical isolation from said inoperable circuits, the identical locations forming a first level standard pattern of said secondary signal-connect means in the partial circuit integration that is identical for each of said integrated circuit members; and

means on each of said integrated circuit members for defining a second level layer of said electrical conductor means selectively coupled to said secondary signal-connect means in the first level standard pattern and routed from said secondary signal-connect means in substantial electrical isolation from said first level layer of said electrical conductor means in a second level standard pattern that is identical for each of said integrated circuit members for forming a third level standard pattern that is identical for each of said integrated circuit members for electrically interconnecting said primary signal-connect means of said selected operable circuits into a specific more complex circuit type.

17. The improvement of claim 16 for each of said integrated circuit members in which the number of the identical locations forming the first level standard pattern of said secondary signal-connect means is less than the total number of said primary signal-connect means of said selected operable circuits on each of said integrated circuit members.

18. The improvement of claim 17 for each of said integrated circuit members in which the density of the identical locations forming the first level standard pattern of said secondary signal-connect means varies in accordance with the statistically expected density of the distribution of said selected operable circuits on each of said integrated circuit members at the superposed primary and secondary signal-connect means thereof.

19. The improvement of claim 16 for each of said integrated circuit members in which said electrical conductor means of said first level layer means further includes interconnected electrical conductor line segments positioned at selected areas through which no electrical conductors are routed and none of said primary signal-connect means are positioned, said first level electrical conductor line segments connected to said electrical conductor means of said second level layer means by crossing under said second level layer means.

20. In a unitary integrated circuit member capable of performing an electrical function and having a plurality of functionally separate circuits located thereon, in which some of said functionally separate circuits are usable and the remainder are unusable and in which said usable and unusable circuits have random positions differing from similar functionally separate usable and unusable circuits on other unitary integrated circuit members capable of performing the same electrical function, and in which each of said circuits have means for defining a plurality of individual signal-connects at a first level of metalization, the improvement in providing at least a partially integrated interconnection of said usable circuits having a standard pattern of identical locations of means for defining second individual signal-connects, said usable circuits being selected from any of said usable circuits irrespective of their positions on any of said circuit members, and said standard pattern being the same for all of said circuit members, comprising:

a first layer of dielectric material on said circuit member at the first level having a plurality of means for defining apertures formed therethrough for exposing only said individual signal-connect means of said selected usable circuits;

a first metalization layer of electrical conductors formed on said first layer of dielectric material, said conductors including interconnected line segments configured into at least said partially integrated interconnection and extending from said individual signal-connect means of said selected usable circuits exposed by said aperture means to a plurality of said second individual signal-connect means at the identical locations for forming at least said partially integrated interconnection having the standard pattern on a second level, and for configuring the standard pattern of the circuit locations common to all of said integrated circuit members;

at least some of said second individual signal-connect means being located substantially vertically above corresponding ones of said first level signal-connect means; and

alternate layers of further dielectric material and metalization material on said first layers, each of said alternate layers including a second layer of dielectric material formed on said first layer of conductors having means for defining a plurality of second apertures formed therethrough at the standard pattern locations for exposing only said second signal-connect means, and a second metalization layer of electrical conductors formed on said second layer of dielectric material, said electrical conductors of said second metalization layer configured in further circuit integration of said selected usable circuits for defining a routing thereof in a second standard pattern common to all of said integrated circuit members having appropriate signal-connect means and for interconnecting said selected usable circuits into a specific more complex circuit type.

21. A plurality of integrated circuit members each capable of performing the same electrical function and each comprising:

a plurality of functionally separate circuits on each of said circuit members in which some of said circuits are used and the remainder are unused and in which said used and said unused circuits are randomly positioned on each of said circuit members;

means for defining partial integration of at least one of said used circuits into the electrical function and having a plurality of secondary signal-connect areas, said partial integration means having a configuration and said secondary signal-connect areas having locations which are common to all of said circuit members having the same electrical function, and at least some of said secondary signal-connect areas being located substantially vertically above corresponding ones of said used circuits; and

electrical conductor means coupling any said used circuit to any said signal-connect area, irrespective of the location of any said used circuit.