Intersystem communication link

• US 4,234,919 A
• Filed: 10/31/1978
• Issued: 11/18/1980
• Est. Priority Date: 10/31/1978
• Status: Expired due to Term

• Current Assignee: Honeywell Information Systems, Inc. (Honeywell International Inc.)
• Original Assignee: Honeywell Information Systems, Inc. (Honeywell International Inc.)
• Inventors: Bradley, John J., Barlow, George J., Lombardo, Ralph M. Jr., Bruce, Kenneth E., Conway, John W., O'Keefe, David B.
• Primary Examiner(s): Smith, Jerry
• Application Number:
  US05/956,385
• Time in Patent Office: 749 Days
• Field of Search: 364/200, 364/900
• US Class Current: 710/306
• CPC Class Codes: G06F 13/36 for access to common bus or bus system
• CPC Class Codes: G06F 13/4027 using bus bridges G06F13/4022 takes precedence
• CPC Class Codes: G06F 13/4213 with asynchronous protocol

Abstract

A logic system referred to as an intersystem link unit (ISL) is provided for accommodating the transfer of binary coded information between two or more communication busses in a data processing system, wherein information including memory and non-memory read and write requests, CPU to CPU interrupts, peripheral control units to CPU interrupts may be transferred between plural communication busses each supporting plural data processing units including plural CPUs without substantially affecting the bus rate of the individual communication busses. Binary coded information from a communication bus is acquired asynchronously, and plural bus communications of different types are accommodated in parallel. The ISL units further may be dynamically reconfigured to provide for a reallocation of communication bus resources between communication busses.

Claims

1. An intersystem communication link for use in a data processing system having plural intersystem communication links for accommodating the transfer of information between plural communication busses each providing a common information path for data processing devices electrically interfacing therewith, which comprises:

(a) asynchronous information acquisition means for capturing at the bus rate binary information presented on a first one of said communication busses wherein each type of bus communication is stored in a separate one of plural dedicated file locations included in said acquisition means thereby accommodating plural bus communications of different types in parallel;

(b) information decoding means in electrical communication with said acquisition means for identifying substantially at said bus rate binary information to be further processed by said intersystem link;

(c) information translation means in electrical communication with said acquisition means for selectively converting substantially at said bus rate address information presented on said first bus to address information pertaining to a second, remote one of said communication busses, and address information pertaining to said second bus to address information pertaining to said first bus; and

(d) logic control means in electrical communication with said decoding means, said translation means, and said acquisition means and responsive to detection of first control signals on said first bus by said acquisition means for effecting a selective reconfiguration of said intersystem link and further responsive to the detection of second control signals on said first bus by said acquisition means for controlling the transfer of information through said intersystem link to said remote second bus.

2. The intersystem communication link of claim 1 wherein said information acquisition means further includes:

(a) data register file means responsive to control signals on said first bus and to said logic control means for storing data in selected ones of said plural dedicated file locations; and

(b) address register file means responsive to control signals on said first bus and to said logic control means for storing address information in selected ones of said plural dedicated file locations.

3. The intersystem communication link of claim 1 wherein said decoding means further includes:

(a) intersystem link identification means responsive to address information on said first bus for identifying at the bus rate first half bus cycle requests and second half bus cycle responses from said first bus;

(b) bus comparator means responsive to said acquisition means and to said logic control means for comparing information received from said first bus in a previous bus cycle with information received from said first bus in a current bus cycle, thereby indicating to said logic control means that a response received from said remote second bus may be applied to said first bus;

(c) channel address decoding means responsive to address information for identifying substantially at the bus rate information to be transferred through said intersystem link to non-memory devices; and

(d) memory address decoding means responsive to address information for identifying substantially at the bus rate information to be transferred through said intersystem link to memory devices.

4. The intersystem communication link of claim 1 wherein said information translation means further includes:

(a) memory address translation means selectively converting local memory addresses to remote memory addresses for either directly addressing remote memory devices on said second bus or providing to a remote non-memory device on said second bus a memory address;

(b) destination central processing unit (CPU) address translation means selectively converting local CPU address information to remote CPU address information for addressing remote CPUs, and selectively converting remote address information to local address information for identification by a local CPU; and

(c) source CPU address translation means selectively converting local CPU address information to remote CPU address information for addressing local and remote CPUs.

5. The intersystem communication link of claim 1 wherein said logic control means further includes:

(a) mode control means responsive to said acquisition means for placing said intersystem link in an on-line, clear or stop logic state;

(b) cycle generator means responsive to said acquisition means and said mode control means for selectively generating internal intersystem link timing signals asynchronous to said bus rate to control information flow between said first and second busses;

(c) timing and status logic means responsive to said acquisition means and said cycle generator means for detecting and circumventing information flow deadlocks, and indicating such occurrences;

(d) interrupt means responsive to said timing and status logic means, and in electrical communication with said acquisition means for identifying to said first bus the occurrence of extraneous interrupts in said intersystem link;

(e) function code decoder means responsive to said acquisition means and said cycle generator means for providing a selected one of plural intersystem link operation commands to said mode control means, said timing and status logic means, and said interrupt means; and

(f) RAM counter and control means responsive to said acquisition means and said function code decoder means for selectively reconfiguring said intersystem link.

6. An intersystem communication link for use in a data processing system having plural intersystem communication links for accommodating the transfer of information between plural communication busses each providing a common information path for data processing devices electrically interfacing therewith, which comprises:

acquisition means, including storage means, responsive to first control signals presented on a first one of said communication busses for storing transfer data, also presented on said first bus, in said storage means;

decoder means responsive to said first control signals for generating an enabling signal indicating that said transfer data stored in said storage means is to be transferred to a remote second one of said communication busses;

translation means for translating at least a portion of said transfer data to produce output data having a data format compatible with the data conventions of said remote second bus; and

transfer control means actuated in response to said enabling signal for transferring said output data together with transfer data from said storage means to said remote second bus.

7. The intersystem communication link of claim 6 further comprising:

logic control means coupled to said first bus and responsive to second control signals presented thereon for effecting a selective reconfiguration of said intersystem communication link to modify the data transfer functions thereof.

8. The intersystem communication link of claim 7 wherein said logic control means is constructed and arranged to modify the operation of said translation means after the data conventions of said remote second bus have been changed, whereby said translation means produces output data having a data format compatible with the changed data conventions of said remote second bus.

9. The intersystem communication link of claim 6 further comprising:

means for receiving remote transfer data from said remote second bus;

means included in said translation means for translating at least a portion of said remote transfer data to produce input data having a data format compatible with the data conventions of said first bus; and

means for applying said input data to said first bus to effect a data transaction thereon.

10. The intersystem communication link of claim 6 wherein said storage means includes a plurality of dedicated storage locations and said acquisition means further comprises means for receiving said first control signals and being responsive to different types of said first control signals representing different types of data transactions for storing the transfer data on said first bus in a selected one of said dedicated storage locations depending on the type of first control signal received.