Tester for electronic engine control systems

• US 4,234,921 A
• Filed: 06/27/1978
• Issued: 11/18/1980
• Est. Priority Date: 06/27/1977
• Status: Expired due to Term

• Current Assignee: Tokyo Shibaura Denki Kabushiki Kaisha (Toshiba Corporation)
• Original Assignee: Tokyo Shibaura Denki Kabushiki Kaisha (Toshiba Corporation)
• Inventors: Sato, Kazuyuki, Kinoshita, Tsuneo, Soneoka, Ryusuke
• Primary Examiner(s): Krass, Errol A.
• Application Number:
  US05/919,494
• Time in Patent Office: 875 Days
• Field of Search: 364/551, 364/424, 364/425, 364/431, 364/442, 364/200 MS File, 364/900 MS File, 73/117.2, 73/112, 73/116, 73/117.3, 324/16 R, 324/15, 123/32 EA, 340/22, 340/52 R, 340/53, 340/74
• US Class Current: 701/99
• CPC Class Codes: G01M 15/05 by combined monitoring of two or more different engine parameters

Abstract

A tester for an electronic engine control system is provided with an output circuit through which test signals are delivered to the electronic engine control system. The electronic engine control system responds to the test signals to deliver response signals to the tester. The response signals outputted are sent through an input circuit to a judgement circuit where the response signals are operated upon, compared and judged to check to see whether operation of the engine control system is proper or not. The result of the checking is displayed by a display circuit.

Claims

1. An apparatus for testing an electronic engine control unit wherein the electronic engine control unit receives input signals from a variety of sensors representing the physical conditions of an engine system and wherein the electronic engine control unit generates, in response to the received input signals, response signals to control the operation of the engine system, said testing apparatus comprising:

means for generating signals simulating physical conditions of an engine system;

means for selectively supplying said generated signals as said input signals to said electronic engine control unit;

means for receiving said response signals generated by said electronic engine control unit in response to said input signals supplied to said electronic engine control unit;

means for testing whether said received response signals are within predetermined response limits;

means for indicating the results of said testing determination; and

means for controlling said generating means and said supply means to select the sequence of said simulating signals supplied to said electronic engine control unit and for controlling said receiving means, said testing means and said indicating means to control the indication of the result of the response of said electronic engine control unit to said supplied simulating signals.

2. The testing apparatus of claim 1 wherein said response signals generated by said electronic engine control unit comprise both analogue and digital signals.

3. The testing apparatus of claim 2 wherein said receiving means comprises an analogue signal input circuit and a digital signal input circuit.

4. The testing apparatus of claim 3 wherein said analogue signal input circuit comprises a multiplexer and an analogue-to-digital converter and said digital signal input circuit comprises a buffer register.

5. The testing apparatus of claim 4 wherein said buffer register produces digital outputs and wherein said testing apparatus further includes a mask register for selectively storing the outputs of said buffer register.

6. The testing apparatus of claim 2 wherein said testing means comprises a first circuit for testing the timing of said digital received response signals, a second circuit for testing the threshold level of said analog received response signal, and a circuit for testing the correctness of the predetermined response limits against which said received response signals are tested.

7. The testing apparatus of claim 1 wherein said indicating means comprises a first lamp for indicating that said received response signals are within said predetermined response limits and a second lamp for indicating that said received response signals are outside of said predetermined response limits.

8. The testing apparatus of claim 1 wherein said indicating means comprises a printer for printing the results of said test of said received response signals.

9. The testing apparatus of claim 1 wherein said indicating means comprises a first lamp indicating that said received response signals are within said predetermined response limits, a second lamp for indicating that said received response signals are outside of said predetermined response limits, and a printer for printing the result of said test of said received response signals on a printing medium.

10. The testing apparatus of claim 1 wherein said indicating means comprises a first lamp for indicating that said received response signals are within said predetermined response limits, a second lamp for indicating said received response signals are outside of said predetermined response limits, a printer for printing the results of said test of said received response signals, a magnetic disc unit for recording received response signals which are outside of said predetermined response limits, and data link means adapted to transfer said recorded response signals from said magnetic disc unit to a magnetic disc unit of another testing apparatus.

11. The testing apparatus of claim 1 wherein said control means comprises a central processor unit, input/output means for coupling said central processor unit to (1) said generating means, (2) said supplying means, (3) said receiving means, (4) said testing means, and (5) said indicating means, and a memory means operating as an external bulk memory for said central processor unit and as a main memory for said electronic engine control unit.

12. The testing apparatus of claim 1 wherein said controlling means comprises a central processor unit included in said electronic engine control unit.

13. The testing apparatus of claim 1 wherein said controlling means comprises:

a first input/output bus;

a central processor unit connected through said first input/output bus to said generating means, said supplying means, said receiving means, said testing means, and said indicating means;

a second input/output bus; and

a floppy disc memory unit connected through said second input/output bus to said central processor unit and adapted to store a program to control said central processor unit.

14. An apparatus for testing an electronic engine control unit wherein the electronic engine control unit includes (1) an input circuit for receiving input signals from a variety of sensors which represent the physical conditions of an engine system and (2) an output circuit for outputting response signals generated by said electronic engine control unit in response to said received input signal to control the operation of said engine system, said testing apparatus comprising:

means for generating signals simulating the physical condition of an engine system and for selectively supplying said generated signals to said input circuit of said electronic engine control unit;

means for receiving from said output circuit of said electronic engine control unit said response signals generated by said electronic engine control unit in response to said supplied simulating signals;

first memory means for storing a testing sequence for controlling said generating and supplying means to selectively supply said simulating signals to said electronic engine control unit;

second memory means for storing reference response signals corresponding to said simulating signals and representing acceptable responses to said corresponding simulating signals;

means for comparing said received responses with said reference responses to determine whether said received responses are acceptable;

and means for displaying the results of said comparison to thereby indicate whether said electronic engine control unit is properly responding to input signals simulating the physical conditions of an engine system.

15. The testing apparatus of claim 14 wherein said second memory means comprises a read only memory.

16. The testing apparatus of claim 15 wherein said read only memory is attachable and removable.

17. The testing apparatus of claim 14 wherein said displaying means comprises lamps for displaying the results of said comparisons.

18. The testing apparatus of claim 14 further including a power source supply circuit for supplying power to said testing apparatus, and further wherein said power source supply circuit is adapted to receive power from a battery of an automobile.

19. The testing apparatus of claim 14 wherein said comparing means comprises:

a peak hold circuit for holding the peak value of said received response signal and for generating an output voltage;

voltage dividing resistors for voltage-dividing said output voltage from said peak hold circuit into a high-level voltage and a low-level voltage;

a first analogue-to-digital converter for converting said high-level voltage from analogue to digitial form;

a first register for storing said digital output signal from said first analogue-to-digital converter;

a first comparator for comparing said determined high level voltage with a said response signal and for generating an output signal;

a first integration circuit for integrating the output signal of said first comparing circuit;

a second analogue-to-digital converter for converting the analogue output signal of said first integration circuit to a second digital output signal;

a second register for storing said second digital output signal;

a second comparator for comparing said low-level voltage with a said received response signal;

a second integration circuit for integrating the output signal of said second comparator;

a third analogue-to-digital converter for converting the analogue output signal of said second integration circuit to a third digital output signal;

a third register for storing said third digital output signal;

a fourth analogue-to-digital convertor for producing a fourth digital output signal corresponding to said determined low-level voltage; and

a fourth register for storing said fourth digital output signal.

20. An apparatus for testing an electronic engine control unit wherein the electronic engine control unit includes an input circuit for receiving input signals from a variety of sensors representing the physical conditions of an engine system and further wherein an output circuit provides response signals generated by said electronic engine control unit in response to said received input signals to control the operation of said engine system, said testing apparatus comprising:

a signal-delivering circuit connected to said input circuit of said electronic engine control unit for generating and for supplying simulated sensor signals to said electronic engine control units;

a receiving circuit coupled to said output circuit of said electronic engine control unit for receiving said response signals generated by said electronic engine control unit;

an input/output bus coupled to said signal-delivering circuit and to said receiving circuit;

a central processor unit connected to said input/output bus for receiving said response signals from said receiving circuit over said bus and for testing said received response signals against corresponding reference response signals to determine whether said received response signals are acceptable or not acceptable;

a memory bus coupled to said central processor unit;

a memory connected to said memory bus for storing a program to control said central processor unit and the testing of said response signals received from said electronic engine control unit; and

a display circuit for displaying the results of said test performed by said central processor unit.

21. The testing apparatus of claim 20 wherein said memory is adapted to store a plurality of reference response signals for comparison with response signals generated by a corresponding plurality of electronic engine control units.

22. The testing apparatus of claim 20 wherein said display circuit comprises a first lamp for indicating that said received response signals are acceptable and a second lamp for indicating that said received response signals are unacceptable whereby the electronic engine control unit that generated said received response signals is indicated to be operating acceptably or unacceptably.

23. The testing apparatus of claim 20 wherein said signal-delivering circuit comprises:

programable means for generating a first digital pulse train and a second digital pulse train;

a first memory for storing peak value signals in digital form at addressable memory locations;

a pulse counter for counting said pulses in said first digital pulse train and for addressing said first memory according to the count in said pulse counter to output from said first memory a said stored digital peak value;

first digital-to-analogue converter means for converting to analog form said digital peak value signal outputted from said first memory;

24. a second memory for storing digital waveform values and for outputting a said stored digital waveform value in response to the digital pulses in said second digital pulse train;

a second digital-to-analog converter for converting said outputted digital waveform to an analog signal; and

a multiplier for multiplying the output of said first digital-to-analog converter by the output of said second digital-to-analog converter.

26. The testing apparatus of claim 24 further including means for controlling said addressing means to sequentially address said instructions stored in said first memory means and to selectively address a corresponding instruction in said sequence of reference instructions stored in said second memory means.

25. An apparatus for testing a sample calibration assembly used to control the operation of an electronic engine control unit wherein the electronic engine control unit comprises (1) an input control circuit receiving input signals from a plurality of sensors representing the physical conditions of an engine system, (2) means for generating response signals for controlling the operation of the engine system in response to said received input signals and (3) a circuit for outputting the generated response signals, and wherein the sample calibration assembly comprises a first memory means for storing a sequence of instructions to control said generating means and said electronic engine control unit, said testing apparatus comprising:

a reference calibration assembly comprising a second memory means for storing a reference sequence of instructions for controlling said generating means, said reference sequence of instructions corresponding to said sequence of instructions stored in said first memory means of said sample calibration assembly;

means for selectively addressing said sequence of instructions stored in said first memory means and said corresponding sequence of instructions stored in said second memory means;

means for comparing an addressed instruction from said sequence of instructions stored in said first memory means to its corresponding instruction in said reference sequence of instructions, and for generating an output signal indicating whether said compared instructions are equal or unequal;

means for transferring an addressed instruction in said sequence of instructions stored in said first memory means to said comparing means and an addressed instruction in said reference sequence of instructions stored in said second memory means to said comparing means for comparison thereby; and

means receiving said generated output signal from said comparing means and for indicating whether said compared instructions are equal or unequal.

27. The testing apparatus of claim 25 wherein said receiving and indicating means comprises a first lamp for indicating said compared instructions are equal, a second lamp for indicating said compared instructions are unequal, and means for selectively actuating said first lamp or said second lamp in response to said output signal which represents that said compared instructions are equal or unequal, respectively.