Apparatus for producing pulse width modulated signals

• US 4,236,213 A
• Filed: 11/27/1978
• Issued: 11/25/1980
• Est. Priority Date: 11/27/1978
• Status: Expired due to Term

• Current Assignee: General Motors Corporation (General Motors Company)
• Original Assignee: General Motors Corporation (General Motors Company)
• Inventors: Richardson, James D.
• Primary Examiner(s): Gruber, Felix D.
• Application Number:
  US05/963,694
• Time in Patent Office: 729 Days
• Field of Search: 369/431, 369/442, 369/200, 369/900, 340/167 A, 340/171 PF, 325/142, 325/143, 123/32 EA, 123/32 EC
• US Class Current: 701/102
• CPC Class Codes: B60L 15/08 using pulses
• CPC Class Codes: F02D 41/2403 using essentially up/down counters
• CPC Class Codes: F02D 41/26 using computer, e.g. microprocessor
• CPC Class Codes: H02P 23/0077 Characterised by the use of a particular software algorithm
• CPC Class Codes: Y02T 10/64 Electric machine technologies in electromobility
• CPC Class Codes: Y02T 10/72 Electric energy management in electromobility

Abstract

A microprocessor based engine control system including an engine control unit for producing a plurality of pulse width modulated output signals of programmable frequency. The pulse width and frequency of each output is contained in a control word provided to the engine control unit. The control word contains a pulse width number and a frequency code. The control unit includes a free-running counter and logic means which switches the output signal to one level when the number of stages of the counter defined by the frequency code are all zero and switches the output signal to a second level when the content of the aforementioned number of counter stages is greater than the pulse width modulated number.

Claims

1. Apparatus for generating a pulse width modulated output signal comprising means for storing a control word having a first portion and a second portion, free-running counter means, logic means responsive to the content of said counter means and to said control word, said logic means producing a set pulse width command when a selectable number of bits of said counter means are all the same binary value, said logic means producing a clear pulse width command if the magnitude of said selectable number of bits of said counter means bear a predetermined relationship to the magnitude of a corresponding number of bits of said first portion of said control word, said logic means responsive to the second portions of said control word for selecting the number of bits of said counter utilized in producing said set pulse width and said clear pulse width command, and bistable switching means responsive to said set pulse width and clear pulse width commands for producing an output signal which is at one level in response to said set pulse width command and at a second level in response to said clear pulse width command whereby the pulse width of the output signal is defined by said first portion of said control word and the frequency of the output signal is defined by said second portion of said control word.

2. An engine control system comprising microcomputer means responsive to engine operating conditions for developing a control word having a first portion specifying the pulse width of an output signal and a second portion specifying the frequency of said output signal,

free-running counter means,

logic means including detector means for detecting the state of a selected number of bits of said counter means, comparator means for comparing said selected number of bits of said counter means with said first portion of said control word, and decoding means responsive to the second portion of said control word for selecting the number of bits of said counter means to be detected and compared;

said logic means producing a set pulse width command if the selected bits of said counter means are all the same state, said logic means producing a clear pulse width command if the selected bits of said counter means have a value equal to or greater than the value of a corresponding number of bits of said first portion of said control word,

bistable switching means responsive to said set pulse width and clear pulse width commands for producing a bilevel output signal having a pulse width defined by said first portion of said control word and a frequency defined by said second portion of said control word, and

actuating means responsive to said output signal for affecting the operation of said engine.

3. An engine control system comprising microcomputer means responsive to engine operating parameters for developing a control word having a first portion specifying the pulse width of an output signal and a second portion specifying the frequency of said output signal,

an engine control unit coupled to said microcomputer means for data exchange therewith and including at least one RAM register for storing said control word, free-running counter means, logic means including detector means, comparator means, decoding means and sequence control logic, said sequence control logic transferring said control word from said RAM register to said logic means each time said counter means is incremented, said decoding means responsive to the second portion of said control word for selecting a certain number of bits of said counter means, said detector means producing a set pulse width command if the selected bits of said counter means are all at the same state, said comparator means producing a clear pulse width command if said selected bits of said counter means have a value equal to or greater than a corresponding number of bits of said first portion of said control word,

bistable switching means responsive to said set pulse width and clear pulse width commands for producing a bilevel output signal having a pulse width defined by said first portion of said control word and a frequency defined by said second portion of said control word, and

actuator means responsive to said output signal for affecting the operation of said engine.

4. An engine control system comprising microcomputer means responsive to engine operating parameters for developing a control word for each of a plurality of output devices affecting the operation of the engine,

an engine control unit coupled to said microcomputer means for data exchange therewith and including a plurality of RAM registers adapted to be loaded with respective ones of said control words by said microcomputer means, free-running counter means, each of said control words having a first portion thereof defining the pulse width of an output signal in terms of the state of a specified number of bits of said counter means, each of said control words having a second portion thereof defining said number of bits of said counter means, logic means including means for decoding the second portion of said control word and for producing a set pulse width command if the specified number of bits of said counter are at the same logic level and for producing a clear pulse width command if the specified number of bits of said counter have a value greater than the value of a corresponding number of bits of the first portion of said control word,

a plurality of bistable switching means controlling respective ones of said output devices and responsive to said set pulse width and clear pulse width commands for producing a bilevel output having a pulse width and frequency defined by said control word, and

means for sequentially transferring said plurality of control words from said registers to said logic means and for selecting a corresponding one of said bistable switching means for receipt of said commands.

5. An engine control system comprising a microcomputer, means providing input data to said microcomputer, said microcomputer adapted to develop a plurality of control words defining desired engine operating conditions in response to said input data,

an engine control unit coupled to said microcomputer for data exchange therewith and including a counter, means for continuously clocking said counter, a plurality of RAM registers adapted to be loaded with respective ones of said control words by said microcomputer, a plurality of bistable output devices corresponding to respective ones of said RAM registers and responsive to a set pulse width command and a clear pulse width command for producing a bilevel output signal, logic means responsive to said control word and the state of said counter means for producing said set and clear pulse width commands, each of said control words having a first portion containing a pulse width number and a second portion containing a coded representation of the number of bits of said counter to be utilized by said logic means in producing said commands, microprogrammed control means, means providing a fixed frequency input to said microprogrammed control means, said microprogrammed control means sequentially transferring the content of said plurality of RAM registers to said logic means and selecting a corresponding one of said output devices in response to said fixed frequency input, said logic means producing said set pulse width command if the number of bits of said counter means specified by the code in said second portion of said control word are all the same value and producing said clear pulse width command if the count represented by the said number of bits of said counter means is greater than the pulse width number contained in said first portion of said control word.

6. An engine control system comprising computer means responsive to engine operating conditions for developing a control word defining a desired operating condition of the engine,

a microprogrammed control unit for developing an output signal in accordance with said control word,

an address bus and a data bus coupling said computer means to said control unit to permit transfer of data including said control word between said control unit and said computer means,

said control unit including an internal data bus,

read/write memory means coupled to said internal data bus, an arithmetic logic unit (ALU) having first and second inputs and an output, said first input being coupled to said internal data bus,

free-running counter means,

means connecting the output of said counter means to said second input of said ALU,

read only memory means having a plurality of addressible locations each containing a program instruction,

program counter means coupled with said read only memory for sequentially addressing said locations,

request logic responsive to at least one input for loading said program counter with a starting address in said read only memory means,

an instruction register coupled to said read only memory means for storing the instructions addressed by said program counter,

multiplexer means coupled to said computer and to said instruction register for permitting selective access to said read/write memory by said computer and said read only memory means under the control of said computer,

bistable output means,

decode logic coupled with said instruction register for establishing internal data paths within said control unit as specified by the instruction in said instruction register,

said ALU including means for performing arithmetic and logic operations relative to the content of said counter means with the content of locations in said read/write memory means and for controlling the state of said bistable output means as a function of the value of the content of said counter means and said control word.

7. An engine control system comprising microcomputer means for producing a control word in response to engine operating conditions, said control word defining a desired operating condition of the engine,

a microprogrammed control unit for producing a pulse width modulated output signal in accordance with said control word,

an address bus, a data bus, and control lines interconnecting said microcomputer means and said control unit to permit data transfer between said microcomputer means and said control unit,

said control unit comprising an internal data bus,

bus interface means connecting said internal data bus to said first mentioned data bus,

read/write memory means connected with said internal data bus for storing said control word,

arithmetic logic means having first and second inputs and an output, said first input being connected with said internal data bus,

free-running counter means,

means for generating a HOLD signal whenever said microcomputer means communicates with said control unit,

means connecting the output of said free-running counter means to said second input of said arithmetic logic means,

read only memory means storing a microprogram including a plurality of instructions,

program counter means connected with said read only memory means for sequencing through said instructions,

request logic means for loading said program counter means with a starting address in said read only memory, said request logic means responsive to an input of predetermined frequency,

an instruction register connected with said read only memory for storing the instructions addressed by said program counter means,

multiplexer means permitting selective access to said read/write memory by said microcomputer means or said microprogram dependent on the state of said HOLD signal,

bistable output means,

decode logic connected with said instruction register for establishing data paths within said control unit as specified by the instruction in said instruction register, said decode logic adapted to control the loading of said program counter means and responsive to said HOLD signal for interrupting the microprogram during transfer of data between said microcomputer and said control unit,

said arithmetic logic means including means for comparing the state of said free-running counter means and the content of a location in said read/write memory means containing said control word and for controlling the state of said bistable output means as a function of the value of the content of said free-running counter means and said control word.

8. Apparatus for generating a pulse width modulated output signal comprising means for storing a control word having a first portion containing a pulse width number and a second portion containing a frequency code, free-running counter means, logic means responsive to the content of said counter means and said control word, said logic means responsive to said frequency code for selecting certain bits of said counter means and certain bits of said first portion of said control word, said logic means producing a first command when said selected bits of said counter means are all the same binary value, said logic means producing a second command when the selected bits of said counter means bear a predetermined relationship to the selected bits of said first portion of said control word, and means responsive to said first and second commands for producing a bilevel output signal.

9. Apparatus for generating a pulse width modulated output signal comprising

a binary counter,

clock means for continuously incrementing said counter,

means for storing a control word having a first portion containing a pulse width number and a second portion containing a coded representation of the number of bits of said counter to be considered in determining the frequency and pulse width of the output signal,

bistable switching means responsive to a set pulse width and a clear pulse width command for producing said output signal,

logic means responsive to said control word and to the state of said counter for producing said set and clear pulse width commands, said logic means producing said set pulse width command when the number of bits of said counter specified by the code in said second portion of said control word are all zero, and producing said clear pulse command when the count represented by said number of bits is greater than the number contained in said first portion of said control word.