Bus arbiter

• US 4,237,534 A
• Filed: 11/13/1978
• Issued: 12/02/1980
• Est. Priority Date: 11/13/1978
• Status: Expired due to Term

• Current Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Felix, Kenneth A.
• Primary Examiner(s): Shaw, Gareth D.
• Assistant Examiner(s): Chan, E.
• Application Number:
  US05/960,321
• Time in Patent Office: 750 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 710/123
• CPC Class Codes: G06F 13/18 based on priority control G06F13/1605 takes precedence
• CPC Class Codes: G06F 13/364 using independent requests or grants, e.g. using separated request and grant lines

Abstract

An improved multiprocessor bus arbiter which provides dynamically prioritized access for a plurality of processors to shared peripheral devices on a common bus through bus access switches. The arbiter includes logic circuitry to which incoming bus access request signals are coupled and a memory means which stores bus access status. The logic circuit determines bus access based on the input request signal and the stored information. The arbiter is adapted to provide a cycle shared mode of access or a lock out mode of access, as may be required.

Claims

1. A bus arbiter for providing, in response to bus access request signals from two or more controllers, dynamically prioritized access to a common bus of a digital system have at least one peripheral device coupled to the common bus, and said two or more controllers coupled to the common bus through respective bus access switching means, said switching means activated by applied present bus access grant signals, the arbiter comprising:

(a) a plurality of logic circuits each having input means coupled to a plurality of decoding AND gates inputs and the outputs of the AND gates are coupled to an OR gate, for generating at the output of the OR gate a future bus access grant signal based on the bus access request signals and one or more present bus access grant signals applied to said input means;

(b) a plurality of memory devices for storing the present bus access grant signal, each of said memory devices coupled to the output of each said OR gate for updating the present bus access grant signal of the memory devices in response to the future bus access grant signal, and each memory device having an output terminal for applying the present bus access grant signal to the bus access switching means; and

(c) direct feedback means for coupling the output terminal of at least one of the memory means to the input memory devices of each logic circuit supply the present bus access grant signal information thereto .

2. The bus arbiter of claim 1, including a control logic circuit, coupled to the memory devices and having input means for input of the present bus access grant signal and bus access request signals, for maintaining a present access grant signal to a particular access switch and to lock out access grant signals to other switches whereby access to the common bus is maintained until the access request signal from the currently accessing controller is removed.

3. The bus arbiter of claims 1 or 2 or 5 wherein each said AND gate is replaced by a NAND gate and each said OR gate is replaced by a NOR gate.

4. The bus arbiter of claims 1 or 2 wherein each memory device comprises a latch.

5. The bus arbiter of claim 1 wherein said arbiter is adapted to operate in a cyclic mode in response to bus access request signals for providing access to the common bus in successive cycles.