Circuit arrangement for establishing weighting coefficients in an analog-type adaptive equalizer

• US 4,241,320 A
• Filed: 08/23/1979
• Issued: 12/23/1980
• Est. Priority Date: 08/25/1978
• Status: Expired due to Term

• Current Assignee: Cselt - Centro Studi E Laboratori Telecommunicazioni SPA
• Original Assignee: Cselt - Centro Studi E Laboratori Telecommunicazioni SPA
• Inventors: Fausone, Alfredo, Rivelli, Renato
• Primary Examiner(s): Gensler, Paul L.
• Application Number:
  US06/069,130
• Time in Patent Office: 488 Days
• Field of Search: 333/18, 333/28 R, 333/166, 307/264, 330/59, 330/144-146, 330/284, 375/14, 375/15
• US Class Current: 333/18
• CPC Class Codes: H04B 3/142 using echo-equalisers, e.g. transversal

Abstract

An adaptive equalizer for a telecommunication system, designed to process high-frequency signals in a band on the order of 50 MHz, comprises several weighting networks with input connections to respective taps of a delay line and with output connections to a summing amplifier, each weighting circuit having a control input to which a selected corrective voltage is applied. Each weighting network includes a bridge with two arms constituted by respective secondaries of an input transformer and two other arms in the form of indirectly variable resistance elements, specifically photoresistors photoelectrically coupled to a pair of light-emitting diodes, capacitively isolated for direct current from other parts of the bridge. Energization of the control input with corrective analog voltage of either polarity unbalances the bridge by differentially exciting the light-conductive diodes through respective operational amplifiers also receiving feedback signals derived from the voltage drops across the associated photoresistors which are traversed by constant currents.

Claims

1. A weighting network for an adaptive equalizer inserted between a transmission channel and a load for processing incoming high-frequency signals by multiplying their amplitudes by selected analog coefficients, comprising:

input means for receiving the high-frequency signals to be processed;

output means for emitting the processed high-frequency signals;

a control terminal for receiving a corrective voltage determining a selected analog coefficient;

a bridge circuit inserted between said input and output means, said bridge circuit including two impedance elements having an electrical resistance indirectly variable by an external energy field;

a source of constant reference current connected to each of said impedance elements for generating a voltage drop, proportional to said resistance, thereacross;

a pair of energy emitters respectively juxtaposed with said impedance elements;

amplifier means connected to said terminal and across said energy emitters for differentially exciting same to unbalance said bridge circuit in response to said corrective voltage; and

feedback means connected between said impedance elements and said amplifier means for stabilizing the excitation of said energy emitters in response to the voltage drop across the respective impedance elements.

2. A weighting network as defined in claim 1 wherein said bridge circuit further includes two impedance arms coupled with said input means for energization in phase opposition by said incoming high-frequency signals, each of said impedance elements being connected to said output means in series with one of said impedance arms.

3. A weighting network as defined in claim 2 wherein said impedance arms are transformer secondaries.

4. A weighting network as defined in claim 2 or 3 wherein said bridge circuit further includes a plurality of blocking capacitors separating said impedance elements from said impedance arms and from said output means.

5. A weighting network as defined in claim 1, 2 or 3 wherein said impedance elements are photoelectrically coupled with said energy emitters.

6. A weighting network as defined in claim 1, 2 or 3 wherein said feedback means comprises a pair of first operational amplifiers each having an inverting and noninverting input connected across one of said impedance elements, said amplifier means comprising a pair of second operational amplifiers each having an inverting input connected to an output of one of said first operational amplifiers and a noninverting input connected to said terminal.