Digital phase lock circuit

• US 4,242,639 A
• Filed: 09/05/1978
• Issued: 12/30/1980
• Est. Priority Date: 09/05/1978
• Status: Expired due to Term

• Current Assignee: NCR Corporation (NCR Voyix Corporation)
• Original Assignee: NCR Corporation (NCR Voyix Corporation)
• Inventors: Boone, James G.
• Primary Examiner(s): Smith, Alfred E.
• Assistant Examiner(s): O'Hare, Thomas P.
• Application Number:
  US05/939,762
• Time in Patent Office: 847 Days
• Field of Search: 328/155, 328/55, 328/25, 328/161, 364/701, 364/703
• US Class Current: 327/160
• CPC Class Codes: H03L 7/0992 comprising a counter or a frequency divider

Abstract

A digital phase lock circuit wherein both the phase and frequency of an output signal are synchronized to an input signal. The present phase lock circuit is comprised of a clock signal source, first, second, and third counters, and a holding register. The first counter is utilized to count a predetermined number of cycles of the input signal to establish a first time period. The second counter receives as another input the clock signal and counts the clocks during the established first time period. The value of counted clocks contained in the second counter at the end of the first time period is divided by the predetermined number of cycles the first counter is set to count, and the result is stored in the holding register. The count in the holding register is used to preset the third counter which is then allowed to count down to zero, at the clock rate. The third counter is preset to the value contained in the holding register at each establishment of the first time period. The cycle time of the third counter is thus synchronized, in phase and frequency, to the incoming signal.

Claims

1. A phase lock circuit comprising:

means for providing an indication signal upon the occurrence of a predetermined number of transitions in an input signal;

means for providing a periodic signal;

first means for dividing the number of periodic signals occurring between successive indication signals by the number of predetermined transitions in the input signal to provide a quotient output signal;

second means for dividing the predetermined number of periodic signals by said quotient output signal to provide a periodic output signal having a frequency and phase corresponding to said input signal; and

a holding register means interposed between said first and said second means for holding the quotient output signal from said first means for use by said second means, said holding register means adapted to reset upon receipt of said indication signal.

2. A phase lock circuit comprising:

a first counter means having an input adapted to receive an input signal and to increment in response to each transition in said input signal, and an output for issuing an output signal each time said first counter reaches a predetermined count;

a clock means for providing a periodic signal wherein the period is substantially less than the period between transitions of said input signal;

second counter means operatively connected to said first counter and said clock source for counting the number of periods of said periodic signal which occur between successive output signals from said first counter and for dividing the count by said predetermined count to provide a divided output signal; and

means for receiving the divided output signal from said second counter and for dividing said periodic signal by said divided output signal, upon receipt of the output signal from said first counter to provide an output signal having a frequency and phase corresponding to said input signal.

3. The phase lock circuit according to claim 2 wherein said means for receiving the output signal is a counter adapted to being set to the count value of said divided output signal, and for incrementing from said count value in response to said periodic signal and reset to the most recent count value in response to said signal from said first counter means.

4. The phase lock circuit according to claim 2 and further comprising:

a holding register means interposed between said second counter means and said means for receiving for holding said divided output signal from said second counter means for use by said means for receiving, said holding register means adapted to reset upon receipt of the output signal from said first counter means.

5. The phase lock circuit according to claim 2 wherein said second counter means is comprised of cascaded binary counters receiving as a counting input said periodic signal and/or a resetting input the output signal from said first counter means, said divided output signal being derived from selected outputs of said counters.

6. A phase lock circuit for synchronizing a loop generated signal in frequency and phase to an input signal, comprising:

first means for receiving an input signal and for providing a signal indicative of the occurrence of a predetermined number of transitions of said input signal;

a clock signal source for providing a train of clock pulses;

second means for counting the number of clock pulses occurring during the period corresponding to the occurrence of a predetermined number of input signal transitions and for providing an output count corresponding to the count of clock pulses divided by the predetermined number of input signal transitions;

third means for receiving and holding the output count from said second means; and

fourth means operatively connected to said first means, said third means, and said clock signal source for generating said loop generated signal by dividing the clock pulses received during the period of each predetermined number of transitions by the count held in said third means.