Method and apparatus for pattern examination

• US 4,242,662 A
• Filed: 03/30/1979
• Issued: 12/30/1980
• Est. Priority Date: 10/16/1978
• Status: Expired due to Term

• Current Assignee: Nippon Telegraph and Telephone Corporation
• Original Assignee: Nippon Telegraph and Telephone East Corporation (Nippon Telegraph and Telephone Corporation)
• Inventors: Saito, Kunio, Kurihara, Kenji, Tsujiyama, Bunjiro
• Primary Examiner(s): Boudreau, Leo H.
• Application Number:
  US06/025,447
• Time in Patent Office: 641 Days
• Field of Search: 340/146.3 H, 340/146.3 MA, 340/146.3 AC, 340/146.3 AE, 364/488-491, 364/515, 250/562, 250/572, 250/563, 250/561
• US Class Current: 382/149
• CPC Class Codes: G01B 11/024 by means of diode-array scanning
• CPC Class Codes: G03F 7/70616 Monitoring the printed patterns

Abstract

A pattern to be examined is scanned to produce binary information of divisional regions of the pattern corresponding to the picture elements of respective scanning lines as parallel information. The parallel information regarding the shape and position of the pattern is concurrently examined under two modes. The second mode includes examination of the vertical edge and the horizontal edge, examination of the vertical and horizontal edges by compensating the deviation of mask setting in the horizontal direction, and examination of the vertical and horizontal edges by compensating the deviation of mask setting in the vertical direction.

Claims

1. A method of examining a pattern comprising the steps of:

(a) detecting a pattern to be examined in accordance with regions of the pattern corresponding to picture elements on scanning lines of a sensor to produce binary video signals respctively from said regions;

(b) memorizing as parallel information the binary video signals in P shift registers having each Q memory elements, said P shift registers being connected in series via delay circuits each consisting of N-Q memory elements, where N is the number of picture elements on one scanning line, Q<

N and P<

N;

(c) fetching said parallel information for logically processing the same so as to generate examination outputs pertaining to the shape and position of the pattern to be examined, said examination output pertaining to the position of the pattern to be examined including examination outputs concerning vertical and horizontal edges of the pattern; and

(d) judging the existence of a horizontal edge when defective pattern position data on the basis of detection of vertical edges is obtained from successive scanning lines of less than a predetermined number.

2. A method of examining a pattern comprising the steps of:

(a) detecting a pattern to be examined in accordance with regions of the pattern corresponding to picture elements on scanning lines of a sensor to produce binary video signals respctively from said regions;

(b) memorizing as parallel information the binary video signals in P shift registers having each Q memory elements, said P shift registers being connected in series via delay circuits each consisting of N-Q memory elements, where N is the number of picture elements on one scanning line, Q<

N and P<

N;

(c) fetching said parallel information for logically processing the same so as to generate examination outputs pertaining to the shape and position of the pattern to be examined, said examination output pertaining to the position of the pattern to be examined including examination outputs concerning vertical and horizontal edges of the pattern; and

(d) judging the existence of a horizontal edge when the value of Σ

xi associated with the subsequent scanning line is different from that associated with the previous scanning line, where Xi represents the distance between a picture element corresponding to the pattern region representative of a vertical edge and a reference point on the respective scanning lines.

3. A method of examining a pattern comprising the steps of:

(a) scanning a pattern region formed with a pattern to be examined to obtain a video signal and then converting the same into a binary video signal;

(b) applying said binary video signal to a plurality (P) of shift registers, the number P being less than the number of scanning lines necessary for producing the binary video signal from the entire area of the pattern, each shift register including Q memory elements connected in series wherein Q is less than N which is obtained by dividing one scanning line of said binary video signal with the length of one picture element, said plurality of shift registers being connected in series through delay circuits having each a delay corresponding to the length of (N-Q) memory elements connected in series;

(c) constituting a first group of memory elements with at least one memory element among Q memory elemetns of an intermediate shift register of said serially connected P shift registers except the first and the last shift registers, at least one memory element among Q memory elements of a shift register between said first and intermediate shift registers, and at least one memory element among Q memory elements of shift register between said last and intermediate shift registers, and simultaneousely deriving out said binary video signals respectively from said plurality of memory elements of said first group to form a first examination parallel binary video signal;

(d) constituting a second group of memory elements with adjoining first and second memory elements among Q memory elements of an intermediate shift register of said serially connected P shift registers, a third memory element among Q memory elements of a shift register between said intermediate shift registers, and a fourth memory element among Q memory elements of a shift register between said intermediate and the last shift registers, and simultaneously deriving out said binary video signals respectively from said memory elements of said second group to constitute a second examination parallel binary video signal;

(e) logically processing said first examination parallel binary video signal to obtain a first examination output representing whether said pattern is a predetermined pattern or not;

(f) producing pattern position information, when the first memory element of said second group is scanned earlier than said second memory element of the same group on one scanning line related to said first and second memory elements thereby producing binary video signals and when the contents of the binary video signals produced by said first and second memory elements differ from each other, by representing the sum of values of a function of the distance between a reference position on said one scanning line and the positions of picture elements corresponding to said first and second memory elements in terms of the number of the picture elements;

(g) comparing said pattern position information with reference pattern position information prepared from design pattern information utilized to form said pattern in said pattern region, thereby obtaining a second examination output representing whether or not said pattern is located at a predetermined position in the direction of scanning said pattern region;

(h) logically processing the parallel binary video signals obtained from said third and fourth memory elements of said second group to produce logically treated binary video signals which, when said third and fourth memory elements are aligned step by step of one picture element length, are utilized to produce a third examination output, said logically treated binary video signals representing whether or not they have different contents at positions on both vertical sides of one picture element, said third examination output representing whether said third and fourth memory elements are at a predetermined position or not in the direction of scanning;

(i) compensating said second examination output with said third examination output in order not to recognize the normal horizontal edge as a defect, producing a fourth examination output; and

(j) producing a final examination output based on said fourth and first examination outputs, said final examination output representing whether said pattern is a predetermined pattern or not and whether said pattern is located at a predetermined position or not.

4. A method of examining a pattern comprising the steps of:

(a) scanning a pattern region formed with a pattern to be examined to obtain a video signal and when converting the same into a binary video signal;

(b) applying said binary video signal to a plurality (P) of shift registers, the number P being less than the number of scanning lines necessary for producing the binary video signal from the entire area of the pattern, each shift register including Q memory elements connected in series wherein Q is less than N which is obtained by dividing one scanning line of said binary video signal with the length of one picture element, said plurality of shift registers being connected in series through delay circuits having each a delay corresponding to the length of (N-Q) memory elements connected in series;

(c) constituting a first group of memory elements with at least one memory element among Q memory elements of an intermediate shift register of said serially connected P shifrt registers except the first and the last shift registers, at least one memory element among Q memory elements of a shift register between said first and intermediate shift registers, and at least one memory element among Q memory elements of a shift register between said last and intermediate shift registers, and simultaneously deriving out said binary video signals respectively from said plurality of memory elements of said first group to form a first examination parallel binary video signal;

(d) constituting a second group of memory elements with adjoining first, second, and fifth and sixth memory elements among Q memory elements of an intermediate shift register of said serially connected P shifrt registers except the first and last shift registers, a third memory element among Q memory elements of a shift register between said first and intermediate shift registers and a fourth memory element among Q memory elements of a shift register between said intermediate and last shift registers, and simultaneously deriving out said binary video signals from the memory elements of said second group to form a second examination parallel binary video signal;

(e) logically processing said first examination parallel binary video signal to obtain a first examination output representing whether said pattern is a predetermined pattern or not;

(f) producing first pattern position information, when the first memory element of said second group is scanned earlier than said second memory element of the same group on one scanning line related to said first and second memory elements thereby producing binary video signals and when the contents of the binary video signals produced by said first and second memory elements differ from each other, by representing the sum of values of a function of the distance between a reference position on said one scanning line and the positions of picture elements corresponding to said first and second memory elements in terms of the number of the picture elements;

(g) comparing said first pattern position information with reference pattern position information prepared from design pattern information utilized to form said pattern in said pattern region thereby obtaining a second examination output representing whether or not said pattern is located at a predetermined position in the direction of scanning said pattern region;

(h) sequentially scanning said fifth, first, second and sixth memory elements of said second group with a scanning line related thereto to produce a binary video signal, and generating second pattern position information when the contents of the binary video signal varies between said first and fifth memory elements, between said first and second memory elements, or between said second and sixth memory elements, said second pattern position information representing the sum of values of a function of the distance between a reference position on said scanning line and the positions of picture elements corresponding to said fifth and first or second and sixth memory elements by the number of the picture elements;

(i) comparing said second pattern position information with reference pattern information prepared from design pattern information utilized to form said pattern in said pattern region to obtain a fifth examination output representing whether or not said pattern is located at a predetermined position in the direction of scanning said pattern region;

(j) logically processing the parallel binary video signal obtained from said third and fourth memory elements of said second group to produce logically treated binary video signals which, when said third and fourth memory elements are aligned step by step of one picture element length, are utilized to produce a third examination output, said logically treated binary video signals representing whether or not they have different contents at positions on both vertical sides of one picture element, said third examination output representing whether said third and fourth memory elements are at a predetermined position or not in the direction of scanning;

(k) compensating said second examination output with said third examination output in order not to recognize the normal horizontal edge as a fault, thus producing a fourth examination output; and

(l) producing a final examination output based on said fourth and first examination outputs, said final examination output representing whether said pattern is a predetermined pattern or not and whether said pattern is locted at a predetermined position or not.

5. A method of examining a pattern comprising the steps of:

(a) scanning a pattern region formed with a pattern to be examined to obtain a video signal and then converting the same into a binary video signal;

(b) applying said binary video signal to a plurality (P) of shift registers, the number P being less than the number of scanning lines necessary for producing the binary video signal from the entire area of the pattern, each shift register including Q memory elements connected in series wherein Q is less than N which is obtained by dividing one scanning line of said binary video signal with the length of one picture element, said plurality of shift registers being connected in series through delay circuits having each a delay corresponding to the length of (N-Q) memory elements connected in series;

(c) constituting a first group of memory elements with at least one memory element among Q memory elements of an intermediate shift register of said serially connected P shift registers except the first and the last shift registers, at least one memory element among Q memory elements of a shift register between said first and intermediate shift registers, and at least one memory element among Q memory elements of a shift register between said last and intermediate shift registers, and simultaneously deriving out said binary video signals respectively from said plurality of memory elements of said first group to form a first examination parallel binary video signal;

(d) constituting a second group of memory elements with adjoining first and second memory elements among Q memory elements of an intermediate shift register of said serially connected P shift registers except the first and the last shift registers, a third memory element among Q memory elements of shift register between said first and intermediate shift registers, and a fourth memory element among Q memory elements of a shift register between said intermediate and last shift registers, and simultaneously deriving out said binary video signals respectively from said memory elements of said second group to form a second examination parallel binary video signal;

(e) logically processing said first examination parallel binary video signal to obtain a first examination output representing whether said pattern signal is a predetermined pattern or not;

(f) producing pattern position information, when the first memory element of said second group is scanned earlier than said second memory element of the same group on one scanning line related to said first and second memory elements thereby producing binary video signals and when the contents of the binary video signals produced by said first and second memory elements differ from each other, by representing the sum of values of a function of the distance between a reference position on said one scanning line and the positions of picture elements corresponding to said first and second memory elements in terms of the number of the picture elements;

(g) comparing said pattern position information with reference pattern position information prepared from design pattern information utilized to form said pattern in said pattern region, thereby obtaining a second examination output representing whether or not said pattern is located at a predetermined position in the direction of scanning said pattern region;

(h) comparing said pattern position information with reference pattern position information which is out of phase by a time corresponding to one scanning time of said second parallel binary video signal to produce a sixth detection output representing whether or not said pattern is located at a predetermined position in the direction of scanning said pattern region;

(i) logically processing the parallel binary video signal obtained from said third and fourth memory elements of said second group to produce logically treated binary video signals which, when said third and fourth memory elements are aligned step by step of one picture element length, are utilized to produce a third examination output, said logically treated binary video signal represenging whether or not they have different contents at positons on both vertical sides of one picture element, said third examination output representing whether said third and fourth memory elements are at a predetermined position or not in the direction of scanning;

(j) compensating said second examination output with said third examination output in order not to recognize the normal horizontal edge as a defect, produceing a fourth examination output; and

(k) producing a final examination output based on said fourth and first examination outputs, said final examination output representing whether said pattern is predetermined pattern or not and whether said pattern is located at a predetermined position or not.

6. Apparatus for examining a pattern comprising:

a pattern examination signal generating unit for scanning a pattern to be examined to produce binary information of divisional regions of said pattern corresponding to picture elements of respective scanning lines as parallel information;

a pattern shape examination circuit unit supplied with said parallel information at timings corresponding to predetermined picture elements on respective scanning lines for examining the detail of said pattern;

a pattern position examining circuit unit supplied with said parallel information at timings corresponding to said predetermined picture elements to exmamine the position of said pattern; and

a computer responsive to examination outputs of said pattern shape examination circuit unit and said pattern position examination circuit unit for producing a reference pattern data to be compared with the examination pattern data produced by said pattern position examination circuit unit, and controlling said pattern examination signal generating unit, said pattern shape examination circuit unit and said pattern position examination circuit unit,

said pattern shape examination circuit unit including a first logic circuit for processing said parallel information, a first gate circuit connected to the output of said logic circuit and operated at a timing corresponding to said predetermined picture element, and a memory circuit for storing the output of said gate circuit which is reset by a pulse synchronized with the scanning line, and

said pattern position detection circuit including a second logic circuit for logically processing parallel information of divisional regions of the pattern corresponding to at least two picture elements on one scanning line, a second gate circuit connected to the output of said second logic circuit, a counter connected to receive the output of said second logic circuit through said second gate circuit for effecting addition only when the output of said second logic circuit is at one level and cleared by said pulse synchronized with said scanning line, a comparator for comparing the output (that is the pattern data) of said counter with said reference data received from said computer through a shift register to produce a first examination output, and a third logic circuit for logically processing parallel information of divisional regions of said pattern corresponding to said picture elements on said one scanning line and picture elements on two scanning lines adjacent to said one scanning line for examining a horizontal edge of said pattern, an NAND gate circuit with one input connected to receive the pattern horizontal edge signal produced by said third logic circuit and the other input supplied with a horizontal edge pattern data formed under control of said computer via a register to produce a second examination output, and an AND gate circuit responsive to said first and second examination outputs for producing a final examination output.

7. Apparatus for examining a pattern according to claim 6 wherein said pattern position detection circuit further comprises a fourth logic circuit for logically processing one of said picture elements on said one scanning line and a picture element adjacent thereto on the same scanning line, a second counter connected to receive the output of said fourth logic circuit through a third gate circuit for effecting addition only when the output of said fourth logic circuit is at one level and cleared by said pulse synchronized with said scanning line, and a comparator for comparing the output of said second counter with a reference data received from said computer through said shift register.

8. Apparatus for examining a pattern according to claim 6 wherein said pattern position detection circuit further comprises a fifth logic circuit for logically processing the other of said picture elements on said one scanning line and a picture element adjacent thereto on the same scanning line, a third counter connected to receive the output of said fifth logic circuit through a fourth gate circuit for effecting addition only when the output of said fifth logic circuit is at one level and cleared by said pulse synchronized with said scanning line, and a comparator for comparing the output of said third counter with a reference data received from said computer through said shift register.