Ternary to binary converter

• US 4,243,976 A
• Filed: 03/12/1979
• Issued: 01/06/1981
• Est. Priority Date: 03/12/1979
• Status: Expired due to Term

• Current Assignee: Singer PLC (Hayleys Plc)
• Original Assignee: Singer PLC (Hayleys Plc)
• Inventors: Weber, Donald J., Warner, Richard C.
• Primary Examiner(s): Miller, Charles D.
• Application Number:
  US06/019,545
• Time in Patent Office: 666 Days
• Field of Search: 340/347 DD, 250/199, 375/38 A, 178/66, 178/67, 178/68
• US Class Current: 341/57
• CPC Class Codes: H04L 25/22 Repeaters for converting two wires to four wires; Repeaters for converting single current to double current

Abstract

A device for converting ternary-coded electrical pulse trains into binary-coded pulse trains, by interrupting a binary zero-rate data stream, representing one ternary condition, to supply an output voltage or no output voltage, representing the other ternary conditions.

Claims

1. A circuit for converting ternary information coded as first and second binary input signals in which a first binary state on one signal and second state on the other signal represent no input, a first binary state on the one and a first binary state on the other represent a positive input and second binary state on one and a second binary state on the other a negative input, into an output signal which, when alternating between two binary states, represents no input, when at a first binary state represents a positive input and when at a second binary state represents a negative input, comprising:

(a) means generating a clock signal synchronous with said first and second input signals;

(b) a multiplexer having as first and second inputs said first and second binary input signals, and providing said first and second signals to first and second outputs, said multiplexer also having control inputs operative to selectively couple said first and second inputs to said first and second outputs;

(c) a first D-type flip flop having said clock signal as a clock input and said first output as a data input and providing said output signal at its output; and

(d) a second D-type flip flop having said clock signal as a clock input and said second output as a data input and providing its outputs to said control inputs of said multiplexer.

2. The ternary to binary converting circuit of claim 1 in which the second flip-flop provides present state and complement of present state information, and the multiplexer chooses and supplies to the first flip-flop either 0, complement of present state, or 1 information, and to the second flip-flop either 0, complement of present state, or present state information, respectively.

3. A circuit for converting ternary information coded as first and second binary input signals in which a first binary state on one signal and second state on the other signal represent no input, a first binary state on the one and a first binary state on the other represent a positive input and second binary state on one and a second binary state on the other a negative input, into an output signal which, when alternating between two binary states, represents no input, when at a first binary state represents a positive input and when at a second binary state represents a negative input, comprising:

(a) means generating a clock signal synchronous with said first and second input signals; and

(b) a memory having at least six word locations, addressable by means of three input terminals, for storing binary signals accessible on two output terminals, said memory being programmed to select and provide an output signal on one output terminal in accordance with said first and second signals applied to two input terminals and a present state of the output signal coupled to the third input terminal from the second output terminal, said memory also having a clock input coupled to said clock signal and providing said output synchronously therewith.

4. The circuit of claim 3 comprising a memory having at least two hundred sixteen word locations, addressable by combinational signals on nine input terminals, for storing binary signals accessible on six output terminals, the memory being programmed to select and provide an output signal on each one of three output terminals in accordance with the input signals on a given pair of input terminals and with a corresponding state of the output signal transmitted to a third, associated input terminal from one of the remaining three output terminals.

5. The circuit of claim 4 in which there are n pairs of input lines, n output lines, 6n! memory locations, and n present state conditions.