Ternary to binary converter
First Claim
1. A circuit for converting ternary information coded as first and second binary input signals in which a first binary state on one signal and second state on the other signal represent no input, a first binary state on the one and a first binary state on the other represent a positive input and second binary state on one and a second binary state on the other a negative input, into an output signal which, when alternating between two binary states, represents no input, when at a first binary state represents a positive input and when at a second binary state represents a negative input, comprising:
- (a) means generating a clock signal synchronous with said first and second input signals;
(b) a multiplexer having as first and second inputs said first and second binary input signals, and providing said first and second signals to first and second outputs, said multiplexer also having control inputs operative to selectively couple said first and second inputs to said first and second outputs;
(c) a first D-type flip flop having said clock signal as a clock input and said first output as a data input and providing said output signal at its output; and
(d) a second D-type flip flop having said clock signal as a clock input and said second output as a data input and providing its outputs to said control inputs of said multiplexer.
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Abstract
A device for converting ternary-coded electrical pulse trains into binary-coded pulse trains, by interrupting a binary zero-rate data stream, representing one ternary condition, to supply an output voltage or no output voltage, representing the other ternary conditions.
32 Citations
5 Claims
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1. A circuit for converting ternary information coded as first and second binary input signals in which a first binary state on one signal and second state on the other signal represent no input, a first binary state on the one and a first binary state on the other represent a positive input and second binary state on one and a second binary state on the other a negative input, into an output signal which, when alternating between two binary states, represents no input, when at a first binary state represents a positive input and when at a second binary state represents a negative input, comprising:
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(a) means generating a clock signal synchronous with said first and second input signals; (b) a multiplexer having as first and second inputs said first and second binary input signals, and providing said first and second signals to first and second outputs, said multiplexer also having control inputs operative to selectively couple said first and second inputs to said first and second outputs; (c) a first D-type flip flop having said clock signal as a clock input and said first output as a data input and providing said output signal at its output; and (d) a second D-type flip flop having said clock signal as a clock input and said second output as a data input and providing its outputs to said control inputs of said multiplexer. - View Dependent Claims (2)
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3. A circuit for converting ternary information coded as first and second binary input signals in which a first binary state on one signal and second state on the other signal represent no input, a first binary state on the one and a first binary state on the other represent a positive input and second binary state on one and a second binary state on the other a negative input, into an output signal which, when alternating between two binary states, represents no input, when at a first binary state represents a positive input and when at a second binary state represents a negative input, comprising:
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(a) means generating a clock signal synchronous with said first and second input signals; and (b) a memory having at least six word locations, addressable by means of three input terminals, for storing binary signals accessible on two output terminals, said memory being programmed to select and provide an output signal on one output terminal in accordance with said first and second signals applied to two input terminals and a present state of the output signal coupled to the third input terminal from the second output terminal, said memory also having a clock input coupled to said clock signal and providing said output synchronously therewith. - View Dependent Claims (4, 5)
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Specification