Semiconductor device

• US 4,243,997 A
• Filed: 10/30/1978
• Issued: 01/06/1981
• Est. Priority Date: 03/25/1976
• Status: Expired due to Term

• Current Assignee: Tokyo Shibaura Electric Co., Ltd.
• Original Assignee: Tokyo Shibaura Electric Co., Ltd.
• Inventors: Masuoka, Fujio, Natori, Kenji
• Primary Examiner(s): Wojciechowicz, Edward J.
• Application Number:
  US05/955,879
• Time in Patent Office: 799 Days
• Field of Search: 357/23, 357/22, 357/55, 357/56, 357/58, 357/90
• US Class Current: 257/330
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1041 with a non-uniform doping structure in the channel region surface
• CPC Class Codes: H01L 29/66613 with a gate recessing step, e.g. using local oxidation making recessed gate LDMOS transistors H01L29/66704
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7834 with a non-planar structure, e.g. the gate or the source or the drain being non-planar

Abstract

The first and second intrinsic semiconductor layers of thickness d are formed on a P type semiconductor substrate, keeping a prescribed interval therebetween, whereby a groove of depth d may be made between these layers. A dielectric layer is formed in such a way that it may cover a base and sides of the groove and a surface of the intrinsic semiconductor layer. On this surface, a gate electrode formed of polysilicon exists. Diffusion regions of a source and a drain of depths X_sj and X_dj are formed, in the neighborhood of groove sides, in the first and second intrinsic semiconductor layers (X_sj, X_dj d), resulting in an MOS transistor.

Claims

1. A semiconductor device comprising a semiconductor substrate of one conductivity type, a source region and a drain region of opposite conductivity type separately provided on the semiconductor substrate to form a conductive channel therebetween, a U-shaped groove provided above said channel between the source and drain regions, said U-shaped groove having side walls of depth d and having a base of breadth L substantially parallel to the direction of said channel, said semiconductor device further having an insulating layer on said groove and a gate electrode installed above the channel on said insulating layer, wherein a depth X_sj of said source region is selected to be calculated by the following formula, ##EQU4## where d=depth of groove

ε

=dielectric coefficient of silicon

N=concentration of impurity of silicon

φ

F=Fermy level

V_B =built-in electric field

V_SUB =voltage of said substrate, and

q=elementary charge,

2. A semiconductor device comprising:

a semiconductor substrate of one conductivity type having a flat surface;

a pair of semiconductor regions of lower conductivity than the conductivity of said substrate, said semiconductor regions being separately provided on said flat surface of said semiconductor substrate, said regions each having a side wall positioned perpendicular to said flat surface and said walls being positioned parallel to each other to define therebetween a U-shaped groove having a base portion defined by a portion of said flat surface, said U-shaped groove forming a conduction channel at said portion of said flat surface of said semiconductor substrate, said semiconductor regions also having bottom surfaces lying in substantially the same plane as that in which said portion of said flat surface is included;

source and drain regions both of opposite conductivity type to said substrate and of greater conductivity than said semiconductor regions formed in one and the other of said pair of semiconductor regions, said source and drain regions being separated from said substrate by said semiconductor regions and from each other by said U-shaped groove between them sufficiently to prevent creation of a short channel effect;

a gate-insulating layer provided on the inner surfaces of said U-shaped groove and;

a controlling electrode provided in said U-shaped groove on said gate-insulating layer.

3. A semiconductor device of claim 2 further including a field-insulating film formed in said substrate and surrounding said U-shaped groove and said pair of semiconductor regions, said field-insulating film being contiguous to said pair of semiconductor regions, the bottom of said field insulating film extending lower into said substrate than said base portion of said U-shaped groove.

4. A semiconductor device according to claim 2, wherein said pair of semiconductor regions are formed to have the opposite conductivity type to said substrate with very low concentration of impurity.

5. A semiconductor device according to claim 2 wherein said pair of semiconductor regions are formed of intrinsic semiconductor layers.

6. A semiconductor device according to claim 3 wherein a P⁺ layer is provided between the lowest part of said field insulating film and said substrate, and said substrate is of P type Si.

7. A semiconductor device of claim 2 wherein said source and drain regions extend to surfaces of said side walls.

8. A semiconductor device comprising:

a semiconductor substrate of one conductivity type having a flat surface;

a pair of intrinsic semiconductor layers separately provided on said flat surface of said semiconductor substrate, said layers each having a side wall positioned perpendicular to said flat surface and said walls being positioned parallel to each other to define therebetween a U-shaped groove having a base portion defined by a portion of said flat surface, said U-shaped groove forming a conduction channel at said portion of said flat surface of said semiconductor substrate, said semiconductor layers also having bottom surfaces lying in substantially the same plane as that in which said flat surface of said substrate is included;

source and drain regions both of opposite conductivity type to said substrate formed on one and the other of said pair of intrinsic semiconductor layers, respectively, in such a manner that said source and drain regions extend to surfaces of said side walls to define portions of said side walls, said source and drain regions being separated from said substrate by said intrinsic semiconductor layers and from each other by said U-shaped groove between them sufficiently to prevent creation of a short channel effect;

a gate-insulating layer provided on the inner surfaces of said U-shaped groove; and

a controlling electrode provided in said U-shaped groove on said gate-insulating layer.

9. A semiconductor device comprising:

a semiconductor substrate of one conductivity type having a flat surface;

a pair of semiconductor layers having a resistance higher than that of said substrate separately provided on said flat surface of said semiconductor substrate, said layers each having a side wall positioned perpendicular to said flat surface and said walls positioned parallel to each other to define there between a U-shaped groove having a base portion defined by a portion of said flat surface, said U-shaped groove forming a conduction channel at said portion of said flat surface of semiconductor substrate, said semiconductor layers also having bottom surfaces lying in substantially the same plane as that in which said flat surface of said substrate is included;

source and drain regions both of opposite conductivity type to said substrate and of less resistance than said semiconductor layers formed on one and the other of said pair of semiconductor layers, respectively, in such a manner that said source and drain regions extend to surfaces of said side walls to define portions of said side walls;

a gate-insulating layer provided on the inner surfaces of said U-shaped groove; and

a controlling electrode provide in said U-shaped groove on said gate-insulating layer.

10. A semiconductor device according to claim 9 wherein said semiconductor layers are of n-type and said substrate is of p type.

11. A semiconductor device according to claim 9 wherein said semiconductor layers are of p-type and said substrate is of n type.

12. A semiconductor device according to claim 9 wherein the thickness of said semiconductor layer adjacent to said source region is formed so as to be thinner than the thickness of said semiconductor layer adjacent to said drain region.