Digital video correlator
First Claim
1. A digital video correlator for comparing a live image with a reference image, comprising:
- digitizing means for dividing the live and reference images into pixels and digitizing said pixels into bits of binary data;
a first shift register connected to said digitizing means for receiving, in sequential order, said bits of binary data of the digitized pixels of the live image;
correlator means interconnected between said digitizing means and said first shift register for receiving and maintaining in sequential order the digitized pixels of the reference image and receiving the digitized pixels of the live image from first shift register, said correlator means comprising second, third, and fourth shift registers, corresponding bits of which are interconnected to a plurality of logic circuit means for producing an output corresponding to an exclusive OR function between corresponding bits of said second and third shift registers logically ANDed with the corresponding bit of said fourth shift register; and
gating circuit means connected to said first, second, third, and fourth shift registers for gating selectable inputs to said registers, said gating means being interconnected between said first shift register and said third shift register for selectively gating binary ones, binary zeros, or the bits of binary data of the live image to said third shift register.
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Abstract
A digital video correlator wherein a reference image and a live image are digitized and compared against each other in a shifting network to determine the correlation or degrees thereof existing between the two images. Fundamentally, the invention includes a video digitizer which divides live and real images from various sources into picture elements and digitizes those elements to fixed voltage levels. The digitized live image is passed to a dynamic memory consisting of a plurality of interconnected shift registers while the digitized reference image is maintained within a first set of shift registers comprising a portion of a processor. A second set of shift registers within the processor maintain therein a mask function. Yet a third set of shift registers within the processor are interconnected in parallel to the dynamic memory to receive, under control of a clock, the digitized data of the live image. As the live image data is shifted through the third set of shift registers, single-bit correlators interconnecting corresponding bits of each of the first, second, and third sets of shift registers, compare the digitized values of the corresponding bits, with such comparison being enabled or negated by the mask function. The outputs of all the single-bit correlators are summed together with that sum indicating the degree of correlation, on a bit-by-bit basis, between the live and reference images. Further circuitry is included to determine the point of best correlation between the two images and to normalize or take the mean value of the correlation output.
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Citations
19 Claims
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1. A digital video correlator for comparing a live image with a reference image, comprising:
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digitizing means for dividing the live and reference images into pixels and digitizing said pixels into bits of binary data; a first shift register connected to said digitizing means for receiving, in sequential order, said bits of binary data of the digitized pixels of the live image; correlator means interconnected between said digitizing means and said first shift register for receiving and maintaining in sequential order the digitized pixels of the reference image and receiving the digitized pixels of the live image from first shift register, said correlator means comprising second, third, and fourth shift registers, corresponding bits of which are interconnected to a plurality of logic circuit means for producing an output corresponding to an exclusive OR function between corresponding bits of said second and third shift registers logically ANDed with the corresponding bit of said fourth shift register; and gating circuit means connected to said first, second, third, and fourth shift registers for gating selectable inputs to said registers, said gating means being interconnected between said first shift register and said third shift register for selectively gating binary ones, binary zeros, or the bits of binary data of the live image to said third shift register. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. Apparatus for comparing bits of binary data of a reference image with bits of binary data of a live image, comprising:
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a first shift register receiving and maintaining bits of binary data of the reference image; a second shift register shifting the bits of binary data of the live image therethrough under control of a clock; a plurality of logic circuits, one interconnected between corresponding bits of each of said first and second shift registers, for producing output signals corresponding to the correlation between said corresponding bits; a summing circuit interconnected to each of said plurality of logic circuits and summing said output signals to produce a correlation signal as an aggregate of said output signals; and a mask generator connected to a third shift register, corresponding bits of said third shift register being connected to the corresponding ones of said logic circuits which are connected to corresponding bits of said first and second shift registers. - View Dependent Claims (12, 13, 14, 15)
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16. A digital video correlator for comparing a live image with a reference image, comprising:
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digitizing means for dividing the live and reference images into pixels and digitizing said pixels into bits of binary data; a first shift register connected to said digitizing means for receiving, in sequential order, said bits of binary data of the digitized pixels of the live image; correlator means interconnected between said digitizing means and said first shift register for receiving and maintaining in sequential order the digitized pixels of the reference image and receiving the digitized pixels of the live image from said first shift register, said correlator means comprising second, third, and fourth shift registers, corresponding bits of which are interconnected to a plurality of logic circuit means for producing an output corresponding to an exclusive OR function between corresponding bits of said second and third shift registers logically ANDed with the corresponding bit of said fourth shift register; gating circuit means connected to said first, second, third, and fourth shift registers for gating selectable input to said registers, said gating means being interconnected between said first shift register and said third shift register for selectively gating binary ones, binary zeros, or the bits of binary data of the live image to said third shift register; and wherein outputs of each of said logic circuit means are summed in a summing circuit and further including a divider circuit interconnected to said summing circuit for dividing the sum achieved by said summing circuit when a first set of inputs are selected by said gating circuit means by the sum achieved by said summing circuit when a second set of inputs are selected by said gating circuit means. - View Dependent Claims (17)
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18. A digital video correlator for comparing a live image with a reference image, comprising:
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digitizing means for dividing the live and reference images into pixels and digitizing said pixels into bits of binary data; a first shift register connected to said digitizing means for receiving, in sequential order, the digitized pixels of the live image; correlator means interconnected between said digitizing means and said first shift register for receiving and maintaining in sequential order the digitized pixels of the reference image and receiving the digitized pixels of the live image from said first shift register, said correlator means comprising second, third, and fourth shift registers, corresponding bits of which are interconnected to a plurality of logic circuit means for producing an output corresponding to an exclusive OR function between corresponding bits of said second and third shift registers logically ANDed with the corresponding bit of said fourth shift registers; gating circuit means connected to said first, second, third, and fourth shift registers for gating selectable inputs to said registers; and a mask generator connected to said gating means, said gating means masking the bits of binary data of the reference image gated to said second shift register. - View Dependent Claims (19)
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Specification