Information processing system

• US 4,245,301 A
• Filed: 08/02/1978
• Issued: 01/13/1981
• Est. Priority Date: 08/03/1977
• Status: Expired due to Term

• Current Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
• Original Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
• Inventors: Aoyagi, Keizo, Shiraogawa, Yukio, Hiraoka, Takashi, Nakajima, Yutaka, Rokutanda, Takashi
• Primary Examiner(s): Ruggiero, Joseph F.
• Application Number:
  US05/930,406
• Time in Patent Office: 895 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 710/107
• CPC Class Codes: G06F 13/362 with centralised access control
• CPC Class Codes: G06F 13/4027 using bus bridges G06F13/4022 takes precedence
• CPC Class Codes: G06F 13/4031 with arbitration
• CPC Class Codes: G06F 15/161 Computing infrastructure, e.g. computer clusters, blade chassis or hardware partitioning casings, cabinets, racks or drawers for data centers H05K5/00

Abstract

An information processing system having a main memory unit, an arithmetic control unit, and a plurality of input/output units, is comprised of a first bus, which is bidirectional, commonly connecting the main memory unit, the arithmetic control unit, and at least one input/output unit, a bus controller for controlling data transfer between two units connecting to the first bus, a second bus, which is also bidirectional, commonly connecting to the arithmetic control unit with at least another input/output unit, and a bus control means which is provided in the arithmetic control unit and controls data transfer between two units connecting to the second bus. The information processing system uses various units connecting to the first and second buses in time sharing and multiplexing mode.

Claims

1. An information processing system including a main memory unit, arithmetic control unit and a plurality of input/output units;

a first bidirectional bus through which said main memory unit, said arithmetic control unit and at least a first of said plurality of input/output units are commonly connected;

a bus controller adapted to manage a first bus access requirement relative to said main memory unit, said arithmetic control unit and said first input/output unit;

one unit of said main memory unit, said arithmetic control unit and said first input/output unit functioning as a master unit and another of said units functioning as a slave unit under the control of the bus controller whereby data is transferred between said master and slave units;

said bus controller including means for processing a bus request from said arithmetic control unit and for granting said request, whereupon said arithmetic control unit and a slave unit are directly coupled via said first bus for the transfer of address and data information therebetween;

a second bidirectional bus through which said arithmetic control unit and a second input/output unit are commonly connected; and

bus control means provided in said arithmetic control unit to control data transfers between said units connected to said second bidirectional bus.

2. An information processing system according to claim 1, in which the respective units connected to said first and second busses are used in time sharing and multiplexing modes.

3. An information processing system according to claim 1, in which said first bus permits data transfer at a high speed.

4. An information processing system according to claim 1, in which said bus controller controls said main memory unit, said arithmetic control unit and said first input/output unit and said units are operable as either master or slave under control of said bus controller.

5. An information processing system according to claim 1, in which said bus controller comprises a first bus interface circuit for controlling data transfer between any two units selected from said main memory unit, said arithmetic control unit and said first input/output unit, and further comprising a zone controller in which writing or reading operations may be carried out for a desired unitary number of bytes to and from the main memory unit.

6. An information processing system according to claim 5, in which said first bus interface circuit comprises an interrupt control circuit for controlling an interrupt request, a bus attainment circuit for coupling a master unit with a slave unit, and a data transfer control circuit for controlling data transfer between said master and said slave units.

7. An information processing system according to claim 5, in which said bus controller comprises means for generating a signal permitting use of said first bus when said first bus is released for a first bus request from said master unit, means for generating a signal to maintain the right to use said first bus, means for checking as to whether said slave unit is operable or not, means for specifying the mode of operation between said master and slave units, and means for controlling data transfer between said master and slave units in accordance with said specified operation mode.

8. An information processing system according to claim 7, in which, when the operable state of said slave unit is checked and, as a result of the check, said slave unit cannot respond, a specific signal is returned to said master unit and said master unit, upon receipt of said specific signal, releases said first bus and, after a given time, obtains again said first bus to check as to whether said slave unit is operable or not.

9. A multi-processing system comprising a plurality of information processing systems, each information processing system comprising:

a first bidirectional bus through which said main memory unit, said arithmetic control unit and at least a first of said plurality of input/output units are commonly connected;

a bus controller adapted to manage a first bus access requirement relative to said main memory unit, said arithmetic control unit and said first input/output unit;

one unit of said main memory unit, said arithmetic control unit and said first input/output unit functioning as a master unit and another of said units functioning as a slave unit under the control of the bus controller whereby data is transferred between said master and slave units;

said bus controller including means for processing a bus request from said arithmetic control unit and for granting said request, whereupon said arithmetic control unit and a slave unit are directly coupled via said first bus for the transfer of address and data information therebetween;

a second bidirectional bus through which said arithmetic control unit and a second input/output unit are commonly connected;

bus control means provided in said arithmetic control unit to control data transfers between said units connected to said second bidirectional bus; and

in which the first busses of the plurality of information processing systems are linked through a computer system linkage device.

10. A multiprocessing system according to claim 9, further comprising means by which said arithmetic control unit in one system accesses said main memory unit of another system, means in which said arithmetic control unit drives said input/output unit in one system and the data transfer is carried out to the main memory unit of another system, means in which said arithmetic control unit in one system drives said input/output unit in another system and the data transfer is carried out to the main memory unit of the former or the latter system, and means for transferring an interrupt between said arithmetic control units.