Digital control system and a method of transmitting control data in such a system

• US 4,246,611 A
• Filed: 06/09/1978
• Issued: 01/20/1981
• Est. Priority Date: 06/21/1977
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Davies, Colin J.
• Primary Examiner(s): Stewart, David L.
• Application Number:
  US05/914,109
• Time in Patent Office: 956 Days
• Field of Search: 358/194, 250/199, 343/178, 179/15 BS, 178/69.1
• US Class Current: 348/734
• CPC Class Codes: H03J 1/0033 for voltage synthesis with a D/A converter

Abstract

TV low cost remote control system using a microprocessor decoder. Control data is transmitted in digitally encoded form and comprises blocks of eight bits of data separated by gaps in transmission of equivalent length. Each data block consists of a start bit followed by seven bits of data for channel identification. Data is presented to the microprocessor on one input line which it samples regularly as a part of its main keyboard scan routine and in response to a start bit checks the data bits and gaps to determine presence of a valid command. The remote control information is decoded directly by the microprocessor. Using seven identification bits, a channel capacity of 128 channels is possible.

Claims

1. A digital control system having control apparatus for providing output control signals in response to signals generated by signal input means, and means operatively coupling the signal input means with said control apparatus and responsive to a single input from the signal input means to generate a group of serial data bits occupying a predetermined number of equal bit periods and comprising an initial predetermined start signal followed by serial data bits identifying that particular input and to transmit to the control apparatus a predetermined number of repetitions of said serial data bit group separated by constant signal level gaps occupying a predetermined series of equal bit periods providing means for verification of valid timing of the group of serial data bits;

and said control apparatus including microprocessor means for checking said gaps to verify valid timing of said groups of serial data bits and responsive to a plurality of validly timed identical groups of serial data bits to generate a corresponding decoded digital output signal.

2. A system according to claim 1, in which the predetermined start signal corresponds to a binary 1.

3. A digital control system according to claim 1 or claim 2, wherein said groups of data bits are separated by gaps each defined by a predetermined series of binary 0 signal levels.

4. A system according to claim 1, wherein said gaps each has a duration equal to that of one of said groups of serial data bits.

5. Digital control system including microprocessor means for providing output signals in response to signals generated by signal input means including a keyboard matrix having m rows and n columns, generator means operatively coupled to the keyboard matrix and responsive to a single input corresponding to actuation of a key of said keyboard matrix to generate a group of serial data bits comprising an initial predetermined start signal followed by identifying data bits corresponding to that particular input, said identifying data bits comprising a data bit in one of n identifying data bit positions designating the matrix column associated with the activated key and the remaining identifying data bits providing coded identification of the matrix row associated with the activated key, and means coupling said generator means to said microprocessor means for transmitting thereto repetitions of said serial data bit groups separated by gaps of predetermined duration for operation of said microprocessor means to produce an output signal.

6. Digital control system according to claim 5, wherein the keyboard matrix has 8 rows, and 4 columns and wherein three identification data bits are used to provide binary coded identification of the matrix row associated with an activated key, and wherein said start signal is a single data bit, and wherein said gaps of predetermined duration are occupied by a data bit different from the start signal data bit.

7. Digital control system according to claim 5, including accumulating means operatively coupled to said microprocessor means for response to recurring identification data bit groups associated with at least one of said matrix keys received by said procroprocessor means, for incrementing or decrementing the count of said accumulating means.

8. Digital control system according to claim 7, including digital to analog converter means for converting the count of said accumulating means into an increasing or decreasing analog signal.

9. Digital control system according to claim 5, wherein said generator means includes counter means clocked at a predetermined rate and operatively coupled to said keyboard matrix for scanning the matrix rows in response to the changing counts of said counter means;

and means for detecting an output from a column of said matrix in response to said scanning when a key is actuated and for combining that output with the then existing digital count of the counter means to produce a said group of identification data bits.

10. Digital control system according to claim 5, wherein said coupling means comprises an electro-opto transmitter means and an optoelectrical receiver means.

11. Digital control system according to claim 10, wherein said transducers comprise semiconductor devices.

12. Digital control system including microprocessor means for providing output signals in response to signals generated by signal input means including a keyboard matrix having m rows and n columns, means operatively coupling the keyboard matrix and said microprocessor means and responsive to a single input corresponding to actuation of a key of said keyboard matrix to generate a group of serial data bits comprising an initial predetermined start signal bit followed by identifying data bits corresponding to that particular input, said identifying data bits comprising a data bit in one of n identifying data bit positions designating the matrix column associated the activated key and the remaining identifying data bits providing coded identification of the matrix row associated with the activated key, said coupling means operable to transmit to said microprocessor means repetitions of said serial data bit groups separated by gaps of predetermined duration with continuation of said repetitions for a predetermined period of time, and wherein said microprocessor means includes means for comparing each group of serial data bits received from said coupling means with the immediately preceding received group and for responding to produce an output signal only on identicality between said groups.

13. Digital control system according to claim 12, wherein said microprocessor means includes timing validity verification means for enabling response of said microprocessor means only to a group of serial data bits following a gap having a duration within a predetermined range of time.

14. Digital control system according to claim 12, wherein said start signal is a binary 1 signal level and said predetermined gaps are occupied by a signal level representing a binary 0.

15. Digital control system including microprocessor means for providing output signals in response to signals generated by signal input means including a keyboard matrix having m rows and n colums;

digital counter means clocked at a predetermined rate and having a set of outputs operatively coupled to said keyboard matrix for scanning the matrix rows in response to the changing count of said counter means;

shift register means having;

(a) at least one stage connected to receiver a digital start signal;

(b) n stages connected to the n respective matrix columns; and

(c) a set of stages connected to the respective outputs of said set of counter outputs coupled to said matrix rows;

means responsive to actuation of a key of said keyboard for loading into said shift register means;

(a) said digital start signal;

(b) a data bit transmitted from said counter via the matrix column associated with said activated key; and

(c) data bits from said set of counter outputs corresponding to the count of the counter means existing at the time of activation of said keyboard key and representing the coded identification of the matrix row associated with the activated key so that said shift register is loaded with a group of serial data bits comprising said row and column identification data bits preceded by said digital start signal;

and means for transmitting to said microprocessor means repetitions of said group of serial data bits from said shift register means separated by gaps of predetermined duration for operation of said microprocessor means to produce an output signal characteristic of the activated key of said keyboard matrix.

16. Digital control system according to claim 15, wherein said transmitting means comprises an electro-opto transmitter means;

and an optoelectrical receiver means for inputting to said microprocessor means, signals received from said transmitting means.

17. Digital control system according to claim 16, wherein said transmitting means and said receiver means comprise semiconductor devices.

18. Digital control system according to claim 15, including signal translating means coupled to said microprocessor means for generating television broadcast receiver control signals in response to output signals from said microprocessor means.

19. Digital control system according to claim 18, including accumulating means operatively coupled to said microprocessor means for response to recurring identification data bit groups associated with at least one of said matrix keys received by said microprocessor means, for incrementing or decrementing the count of said accumulating means.

20. Digital control system according to claim 19, including digital to analog converter means for converting the count of said accumulating means into an increasing or decreasing analog signal.

21. Digital control system according to claim 20, wherein said digital-to-analog converter means provides at least one analog output representing color, volume or brightness control signals.

22. Digital control system according to claim 18, wherein said signal translating means outputs include at least one tuning control output.

23. A method of transmitting control data from an input means to a control apparatus including the steps of:

producing a group of serial data bits including a set of identification bits occupying a predetermined number of equal bit periods for representing a particular control input to the control apparatus and preceded by a predetermined start signal, and for the duration of the control data repeatedly reproducing the start signal and the set of identification data bits, each repetition of the start signal preceding a repetition of said set of identification data bits, and providing between the end of a repetition of a set of the identification data bits and the next repetition of said start signal a gap defined by a predetermined series of equal bit periods occupied by identical signal levels for enabling verification by said control apparatus of valid timing of said groups of serial data bits, said gap having a duration equal to the combined duration of the set of identification data bits together with its start signal.

24. A method according to claim 23, wherein the predetermined start signal is a signal representing a single binary "1".

25. A method according to claim 23, wherein during each said gap there is maintained a data level representing binary "0".

26. A method according to claim 23, wherein each said gap is equal to the combined duration of the set of identification data bits together with its start signal.

27. A method according to claim 23, including the step of using a plurality of validly timed groups of said serial data bits to generate a corresponding decoded digital output signal.

28. A method according to claim 27, including the step of utilizing said decoded digital output signal to produce a television receiver function control signal.

29. A method according to claim 27, including the step of utilizing said decoded digital output signal to produce a television receiver function control signal that varies in an analog manner.

34. A digital control system according to claim 29, including means for accumulating a succession of identical decoded output signals and producing an analog output signal level that increases or decreases with said accumulation.

30. A digital control system having control apparatus including microprocessor means for providing output control signals in response to binary data signals generated by signal input means, and means operatively coupling the signal input means with said control apparatus and responsive to a single input from the signal inputs means to generate a group of serial data bits occupying a predetermined number of equal bit periods and comprising an initial predetermined start signal including a predetermined one of the binary signal levels in the first digit position followed by serial binary data bits identifying that particular input and to transmit to the control apparatus a predetermined number of repetitions of said serial data bit groups separated by gaps occupying a predetermined series of equal bit periods in which only the other binary signal level appears providing means for verification of valid timing of the group of serial data bits, said microprocessor means operable to check said gaps to verify valid timing of said groups of serial data bits and responsive to a plurality of validly timed identical groups of serial data bits to generate a corresponding decoded digital output signal.

31. A digital control system according to claim 30, wherein the start signal is a binary "1" signal level occupying the first digit position and wherein each gap is defined by a series of binary "0" signal levels.

32. A digital control system according to claim 30, further including means for storing said decoded output signals.

33. A digital control system according to claim 31, including means for receiving and utilizing said decoded output signals.