Semiconductor integrated amplifier
First Claim
1. An amplifier circuit having a p-channel type MISFET and an n-channel type MISFET which are integrated in a single semiconductor substrate, a load resistance connected between the drain regions of said MISFETs, a power source to which said MISFETs are connected in series, and a capacitance through which the gates of said MISFETs are connected to each other, characterized by comprising said capacitance having one terminal constituted by a well formed in said semiconductor substrate and another electrode constituted by a gate electrode formed on the surface of said well, said gate electrode and said semiconductor substrate being connected to the high voltage side of the power supply while said well is connected to the low voltage side of the power supply.
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Accused Products
Abstract
A semiconductor integrated amplifier having a p-channel type MISFET and an n-channel type MISFET which are integrated in a single semiconductor substrate, a load resistance connected between the drain regions of the MISFETs, a power source to which the MISFETs are connected in series, and a DC current blocking capacitor through which the gates of the MISFETs are connected to each other. The amplifier has a gate capacitance one terminal of which is constituted by a well formed in the substrate and connected to high voltage side of power supply, while the other electrode thereof is constituted by a gate electrode formed on the well and connected to the low voltage side of the power supply. Parasitic capacitance of the capacitor is considerably reduced to allow a wider range of frequency adjustment of the amplifier.
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Citations
9 Claims
- 1. An amplifier circuit having a p-channel type MISFET and an n-channel type MISFET which are integrated in a single semiconductor substrate, a load resistance connected between the drain regions of said MISFETs, a power source to which said MISFETs are connected in series, and a capacitance through which the gates of said MISFETs are connected to each other, characterized by comprising said capacitance having one terminal constituted by a well formed in said semiconductor substrate and another electrode constituted by a gate electrode formed on the surface of said well, said gate electrode and said semiconductor substrate being connected to the high voltage side of the power supply while said well is connected to the low voltage side of the power supply.
- 4. A semiconductor integrated circuit comprising a semiconductor body having a major surface of a first conductivity type, a first and a second semiconductor region of the second conductivity type formed in the major surface of said body, a first conductivity type MIS transistor formed at the surface of said first region, a second conductivity type MIS transistor formed at the major surface of said body separated from the first and second regions, an insulating film formed on the surface of said second region, a conductive layer formed on the insulating film, means for connecting said second region to the gate electrode of said first conductivity type MIS transistor, and means for connecting said conductive layer to the gate electrode of said second conductivity type MIS transistor, so as to couple both gate electrodes with a capacitor, wherein said first region and said semiconductor body are respectively connected to first and second power source terminals coupled to first and second potentials, respectively, for energizing said first and second conducitivity type MIS transistors to back bias the junction formed between the second region and the semiconductor body to reduce the parasitic capacitance between the second region and the semiconductor body.
Specification