Picture-in-picture television receiver

• US 4,249,213 A
• Filed: 09/11/1979
• Issued: 02/03/1981
• Est. Priority Date: 09/14/1978
• Status: Expired due to Term

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Imaide, Takuya, Masuda, Michio, Kuroyanagi, Tomomitsu
• Primary Examiner(s): Richardson, Robert L.
• Application Number:
  US06/074,761
• Time in Patent Office: 511 Days
• Field of Search: 358/181, 358/182, 358/183, 358/185
• US Class Current: 348/565
• CPC Class Codes: H04N 5/45 Picture in picture , e.g. displaying simultaneously another television channel in a region of the screen

Abstract

A picture-in-picture television receiver is disclosed in which a television picture to be inset is compressed at a compression rate of 1/n and inset as a small-picture in part of a main television picture or large picture, and a single field memory for small-picture reproduction is provided therein in or from which a video signal can be randomly read and written line by line as a unit. In the single field memory is stored the small-picture video signal line by line by the application of a writing clock in which case the time taken in the writing is less than 1/(n+1) of a horizontal period. Then, from the memory is read the stored small-picture information by the application of a reading clock of n times the frequency of the writing clock during the time that writing is not performed, and supplied to be inset in the main television picture. A small-capacity buffer memory is provided at the prestage or following stage of the field memory to prevent the read/write timing overlap in the field memory irrespective of whether the small-picture and the main television picture are synchronized or not in the transmission systems. Thus, the capacity of the field memory essential for the small-picture is about a half of the conventional one.

Claims

1. A picture-in-picture television receiver having a first-television picture tuner and a first I-F amplifier/detector for receiving a program of a first television picture, a second-television picture tuner and a second I-F amplifier/detector for receiving another program of a second television picture, a common video signal coupling means, a video signal processing means and a display means, and in which the second television picture is compressed at a reduction rate of 1/n (n:

positive integers) and inset as a small picture in part of the first television picture, said picture-in-picture television receiver comprising;

(a) a single field memory means coupled between said second I-F amplifier/detector and said common video signal coupling means and capable of randomly reading and writing a video signal of the second television picture each horizontal scanning period as a unit, and

(b) memory control means responsive to sychronizing signals of said first and second television pictures for generating a first clock signal and a second clock signal whose frequency is n times the frequency of said first clock signal, said first clock signal being supplied to said field memory for writing therein contents of said small picture each horizontal scanning period, said second clock signal being supplied to said field memory for reading out the contents stored in the field memory each horizontal scanning period in no write condition to render the contents of small picture to be supplied to said coupling means for coupling the second television picture signal with the first television picture signal;

whereby the second television picture can be inset in the first television picture.

2. A picture-in-picture television receiver according to claim 1 wherein the time during which said second television picture to be inset is written in said single field memory is selected to be less than (reduction rate of small picture)/{(reduction rate of small picture)+1}=1/(n+1) of the horizontal scanning period.

3. A picture-in-picture television receiver according to claim 1 comprising a memory of which capacity is at least one horizontal period of video signal, between said second I-F amplifier/detector and said field memory, and said memory control means having a means for generating an address signal so that said small-picture signal is once written in said one-line memory and subsequently generating an address signal so that the signal stored in said one-line memory is transferred to said single field memory means while said single field memory means is not in read condition.

4. A picture-in-picture television according to claim 3 wherein said one-line memory is a variable shift register.

11. A picture-in-picture television receiver according to claim 1, 5, 8 or 10 wherein said memory control means comprises a means for detecting the field polarities of the first and second television pictures, a means for detecting, whether the field polarities of the first and second television pictures are the same or not, at the time point preceding by the time from the change of the field polarity of the second television picture to the completion of writing the first one-line information in said memory before the first one-line information is begun to be read from said memory, and, if not the same, incrementing or decrementing by one-line unit an address read from said memory at the top of said small-picture in either of the field polarities, thereby correcting interlacing, a means for detecting the presence or absence of said interlace correction, and a means for detecting coincidence of the write address and read address of said memory, and incrementing or decrementing by one-line unit an address read from said memory in either field polarity of the second television picture in accordance with the presence or absence of said correction, thereby correcting interlacing of the second television picture relative to the first television picture.

5. A television receiver wherein a first television picture is normally reproduced and a second television picture is compressed and inset as a small picture in part of the first television picture, said television receiver comprising:

single field memory means in or from which a video signal of said second television picture can be randomly written or read one horizontal line by line as a unit;

means for controlling the read and write operations of said memory means in response to the synchronizing signals of said first and second television pictures; and

buffer memory means in or from which at least one-horizontal line of a video signal can be written or read line by line and which is connected to the output of said single field memory means;

said memory control means supplying a control signal to said single field memory so that the second television picture video signal is written in said single field memory means, and supplying a control signal to said single field memory and said one-line memory so that part or all of said written signal is read through said at least-one-line memory means, and that the other part thereof is directly read to be inset in said first television picture.

6. A television receiver according to claim 5 wherein said at least-one-line memory means is formed of at least a one-line video memory, and at least one-line video signal written into said one-line memory means from said single field memory is read at a given read timing while said single field memory is not in write condition and inset in the first television picture.

7. A television receiver according to claim 6 wherein a plurality of said horizontal-line memory means are provided for extending the time taken when information is transferred from said single field memory means.

8. A picture-in-picture television receiver wherein a first television picture is normally reproduced and a second television picture is compressed to 1/n and inset in part of the first television picture through a video coupling circuit provided therein, said picture-in-picture television receiver comprising:

a single field memory in or from which a video signal of the second television picture can be written and read at an arbitrary timing;

n one-pixel information storage means which are connected to the output of said single field memory and in or from which information is written and read in sequence; and

memory control means which supplies a control signal to said single field memory means and said storage means in response to the synchronizing signals of said first and second television pictures to thereby control the read and write operations of said single field memory and said storage means;

said memory control means comprising a first clock signal generator which generates a write clock signal to write said second television picture signal in the field memory, means for reading the small-picture signal which has been stored in said single field memory by the application of the first-clock signal during the time except said writing and temporarily writing the read small-picture signal in said n storage means, and a second-clock signal generator for controlling the small-picture signal to be read from the said n storage means, the small-picture signal thus read being supplied to said coupling circuit.

9. A picture-in-picture television receiver according to claim 8 wherein the frequency of the first-clock signal is not lower than the sum of the frequency of the second-clock signal and a predetermined write frequency used when the second television picture signal is written in said single field memory.

10. A picture-in-picture television receiver wherein a first television picture is normally reproduced and a second television picture is compressed to 1/n and inset as a small picture in part of the first television picture, said picture-in-picture television receiver comprising:

(a) first and second tuners for first and second television pictures, respectively;

(b) first and second I-F amplifiers/detectors for the first and second television pictures, respectively;

(c) first and second synchronizing separators for the first and second television pictures, respectively;

(d) an A/D converter for converting the analog output from said second I-F amplifier/detector to a digital signal;

(e) a memory control means for generating a memorywriting first timing signal on the basis of the synchronizing signal from said second synchronizing separator and a memory-reading second timing signal on the basis of the synchronizing signal from said first synchronizing separator, the frequency of said first timing signal being n-times the frequency of said second timing signal;

(f) a one-line buffer memory means in which the second television picture signal converted by said A/D converter is temporarily written by the application of said first timing signal;

(g) a RAM capable of storing a single-field video signal of the second television picture which RAM is connected to the output of said buffer memory means and by which information can be written and read freely line by line as a unit in response to the write and read timing signals from said memory control means;

(h) an D/A converter for converting the digital video signal read from said single field RAM, to an analog signal; and

(i) a video-signal coupling/displaying means for coupling said read analog video signal and the output of said first I-F amplifier/detector and for insetting the second television picture in the first television picture;

said memory control means generating a write timing signal so that the time taken when the second television picture to be inset is written in said single field RAM is less than 1/(n+1) of one horizontal scanning period.