Baseband DC offset detector and control circuit for DC coupled digital demodulator

• US 4,250,458 A
• Filed: 05/31/1979
• Issued: 02/10/1981
• Est. Priority Date: 05/31/1979
• Status: Expired due to Term

• Current Assignee: Hughes Electronics Corporation (Rtx Corporation)
• Original Assignee: Digital Communications Corp.
• Inventors: Wyar, Paul F., Richmond, Robert L.
• Primary Examiner(s): Grimm, Siegfried H.
• Application Number:
  US06/044,143
• Time in Patent Office: 621 Days
• Field of Search: 329/110, 329/112, 329/131, 329/132, 329/133, 375/76, 375/83, 375/84, 375/99
• US Class Current: 329/306
• CPC Class Codes: H04L 25/067 providing soft decisions, i.e. decisions together with an estimate of reliability H04L25/068 and H04L25/069 take precedence; sequence estimation techniques H04L25/03178

Abstract

The digital demodulator produces an information bearing analog signal which is controlled in peak-to-peak amplitude. The signal is coupled to a soft-decision demodulator which provides a multi-bit output representative of magnitude (polarity and amplitude) of the analog signal at a rate determined by the symbol clock derived from the digital demodulator. Logic means produces a logic signal of a first or second type in response to selected multi-bit outputs of the soft-decision demodulator. A logic output of the first type is produced if either the multi-bit output represents an analog signal of one polarity and amplitude greater than a predetermined amplitude, or if the multi-bit output represents an analog signal of the other polarity and amplitude less than an equal predetermined amplitude of the other polarity. The logic output is coupled to an integrating means which produces a control signal representative of deviations of the logic signal of the first type from 50% duty cycle. The deviation from 50% duty cycle determines the amplitude of the DC offset, and the polarity of the deviation determines the polarity of the offset. The output of the detector can be used in a feedback loop to eliminate the DC offset by coupling the control signal to a summing junction, to which is also coupled the analog signal.

Claims

1. A DC offset detector for a DC-coupled digital demodulator generating an information bearing analog signal of controlled peak-to-peak amplitude and a symbol clock comprising:

soft-decision demodulating means responsive to said analog signal and to said symbol clock for providing a repetitive multi-bit output, each such multi-bit output representing polarity and amplitude of said analog signal at different points in time,

logic means responsive to said multi-bit output for producing a logic signal of a first type if said multi-bit output represents either an analog signal of one polarity and greater in amplitude than a predetermined amplitude, or an analog signal of other polarity and amplitude less than an equal predetermined amplitude of said other polarity, and

means responsive to said logic means for producing a control signal representative of deviations of said logic signal of a first type from 50% duty cycle.

2. A DC offset correction circuit for removing DC offset comprising a DC offset detector of claim 1 and further including:

summing means with two inputs, a first input responsive to said control signal and a second input coupled to said analog signal, and producing an output related to the algebraic sum of said inputs.

3. The apparatus of claim 1 in which said demodulator includes two channels of demodulation and thus, provides an I and a Q channel information bearing analog signal and in which:

said soft-decision demodulator means comprises I and Q soft-decision demodulators,

said logic means comprises I and Q logic circuits, each responsive to a corresponding demodulator, and

said means responsive to said logic output comprises I and Q means each responsive to an associated logic means and producing I and Q control signals, respectively.

4. A DC offset correction circuit for correcting DC offset comprising the DC offset detector of claim 3 and further including I and Q summing means, each with two inputs, a first input responsive to an associated control signal and a second input coupled to an associated analog signal, and each said summing means producing an output related to the algebraic sum of said inputs.

5. The apparatus of any of claims 1-4 in which said:

soft-decision demodulator means produces a multi-bit output including a sign representing bit and at least one amplitude representing bit, and said logic means including;

means for ANDing all said at least one magnitude representing bit, to produce an AND output, means for EXCLUSIVE ORing the AND output with said sign representing bit negated, for producing said logic output.

6. The apparatus of any of claims 1-4 in which said means responsive to said logic output comprises an active inverting integrating means with a pair of inputs, one from said logic means and another comprising a fixed reference signal, said integrating means further including an output circuit with scale adjusting means for adjusting said control signal.