Vehicle speed recorder

• US 4,250,487 A
• Filed: 10/27/1978
• Issued: 02/10/1981
• Est. Priority Date: 10/27/1978
• Status: Expired due to Term

• Current Assignee: Robert D. Arnold
• Original Assignee: Robert D. Arnold
• Inventors: Arnold, Robert D.
• Primary Examiner(s): Caldwell, Sr., John W.
• Assistant Examiner(s): Nowicki, Joseph E.
• Application Number:
  US05/955,297
• Time in Patent Office: 837 Days
• Field of Search: 340/53, 340/62, 340/670, 340/798, 340/799, 340/706, 340/722, 346/18, 346/33 D, 364/424, 364/438, 364/565, 324/160, 324/172
• US Class Current: 340/441
• CPC Class Codes: G01P 1/122 Speed recorders
• CPC Class Codes: G07C 5/085 using electronic data carriers

Abstract

Speed data samples from an ordinary digital speedometer are written sequentially into a number of addressed memory locations. Each new entry replaces the oldest entry then in memory. This writing process occurs only when the vehicle is moving, so the memory cannot be erased when the vehicle is at rest. The last writing address used is retained. Any stored data sample may be recalled and displayed by presenting its address. The time-before-vehicle-stop of the displayed recalled data corresponds to the sequential interval between the recalling address and the last-used writing address. In the most convenient modification, the user stepwise specifies the sequential interval and the device produces the appropriate recalling address.

Claims

1. A vehicle speed recorder, comprising:

(a) a speedometer that includes an electronic register containing digital speed data;

(b) a memory for storing in addressed locations a plurality of speed data samples from the speedometer register;

(c) mode control means, responsive to a signal from the speedometer register and having a write mode and a read mode, for controlling the transfer of data to and from said memory;

(d) first indexing means, made operable by a signal from said mode control means only in the write mode, for repeatedly generating the next member of a cyclic sequence of addresses that correspond to the addresses of said memory, whereby the last address so generated is retained until the next address is generated;

(e) writing means, initiated each time said first indexing means generates a new address, for transferring data from the speedometer register to the location in said memory whose address corresponds to that new address, whereby the data in any given location are retained there until new data are transferred to that location;

(f) a speed indicator for displaying speed data selected from said memory;

(g) second indexing means, connected to said memory and having first and second manual actuators that are made operable by a signal from said mode control means only in the read mode, for generating any selected member of the cyclic sequence of addresses, wherein in response to a signal from said writing means said second indexing means selects the address generated by said first indexing means each time a new address is so generated, wherein in response to the first manual actuator said second indexing means selects the next member of the cyclic sequence of addresses, and wherein in response to the second manual actuator said second indexing means selects the preceding member of the cyclic sequence of addresses, whereby at the onset of the read mode said second indexing means will contain the address last generated by said first indexing means and, as long as the read mode prevails, the address contained in said second indexing means may be stepped forward or backward by means of the first or second manual actuators respectively; and

(h) reading means, made operable by a signal from said mode control means only in the read mode, for nondestructively transferring data to said speed indicator from the location in said memory whose address corresponds to the address currently selected by said second indexing means.

2. A recorder as in claim 1, further comprising:

(i) a counter that is caused by a signal from said writing means to be set to zero each time said first indexing means operates, that is decremented by a signal from the first manual actuator, and that is incremented by a signal from the second manual actuator; and

(j) a time-back indicator for displaying the contents of said counter, whereby said time-back indicator will display the interval, in the cyclic sequence of addresses, between the address currently selected by said second indexing means and the address last generated by said first indexing means.

3. A recorder as in claim 2 wherein a signal from said mode control means blanks said time-back indicator when said mode control means is in the write mode.

7. A recorder as in claims 1 or 4, further comprising:

enforcement signal means, responsive to a signal from the speedometer register, for indicating that said vehicle has exceeded a specified speed; and

means, responsive to a signal from said mode control means, for deactivating said enforcement signal means after a fixed time interval after said vehicle stops.

4. A vehicle speed recorder, comprising:

(a) a speedometer that includes an electronic register containing digital speed data;

(b) a memory for storing in addressed locations a plurality of speed data samples from the speedometer register;

(c) mode control means, having a write mode and a read mode, for controlling the transfer of data to and from said memory, wherein said mode control means, responsive to a signal from the speedometer register, switches to the write mode whenever the speedometer register contains nonzero speed data and switches to the read mode, after a delay sufficient to allow one speed data sample to be stored in said memory, when the speedometer register contains zero speed data;

(d) first indexing means, made operable by a signal from said mode control means only in the write mode, for repeatedly generating the next member of a cyclic sequence of addresses that correspond to the addresses of said memory, whereby the last address so generated is retained until the next address is generated;

(e) writing means, initiated each time said first indexing means generates a new address, for transferring data from the speedometer register to the location in said memory whose address corresponds to that new address, whereby the data in any given location are retained there until new data are transferred to that location;

(f) a speed indicator for displaying speed data selected from said memory;

(g) second indexing means, connected to said memory, for generating any selected member of the cyclic sequence of addresses; and

(h) reading means, made operable by a signal from said mode control means only in the read mode, for nondestructively transferring data to said speed indicator from the location in said memory whose address corresponds to the address currently selected by said second indexing means.

5. A recorder as in claim 4, further comprising:

(i) interval determining means, responsive to signals from said writing means and said second indexing means, for generating a number corresponding to the interval, in the cyclic sequence of addresses, between the address currently selected by said second indexing means and the address last generated by said first indexing means; and

(j) a time-back indicator for displaying the number generated by said interval determining means.

6. A recorder as in claim 5 wherein a signal from said mode control means blanks said time-back indicator when said mode control means is in the write mode.