×

Vehicle speed recorder

  • US 4,250,487 A
  • Filed: 10/27/1978
  • Issued: 02/10/1981
  • Est. Priority Date: 10/27/1978
  • Status: Expired due to Term
First Claim
Patent Images

1. A vehicle speed recorder, comprising:

  • (a) a speedometer that includes an electronic register containing digital speed data;

    (b) a memory for storing in addressed locations a plurality of speed data samples from the speedometer register;

    (c) mode control means, responsive to a signal from the speedometer register and having a write mode and a read mode, for controlling the transfer of data to and from said memory;

    (d) first indexing means, made operable by a signal from said mode control means only in the write mode, for repeatedly generating the next member of a cyclic sequence of addresses that correspond to the addresses of said memory, whereby the last address so generated is retained until the next address is generated;

    (e) writing means, initiated each time said first indexing means generates a new address, for transferring data from the speedometer register to the location in said memory whose address corresponds to that new address, whereby the data in any given location are retained there until new data are transferred to that location;

    (f) a speed indicator for displaying speed data selected from said memory;

    (g) second indexing means, connected to said memory and having first and second manual actuators that are made operable by a signal from said mode control means only in the read mode, for generating any selected member of the cyclic sequence of addresses, wherein in response to a signal from said writing means said second indexing means selects the address generated by said first indexing means each time a new address is so generated, wherein in response to the first manual actuator said second indexing means selects the next member of the cyclic sequence of addresses, and wherein in response to the second manual actuator said second indexing means selects the preceding member of the cyclic sequence of addresses, whereby at the onset of the read mode said second indexing means will contain the address last generated by said first indexing means and, as long as the read mode prevails, the address contained in said second indexing means may be stepped forward or backward by means of the first or second manual actuators respectively; and

    (h) reading means, made operable by a signal from said mode control means only in the read mode, for nondestructively transferring data to said speed indicator from the location in said memory whose address corresponds to the address currently selected by said second indexing means.

View all claims
  • 0 Assignments
Timeline View
Assignment View
    ×
    ×