Semiconductor devices having VMOS transistors and VMOS dynamic memory cells

• US 4,250,519 A
• Filed: 08/31/1979
• Issued: 02/10/1981
• Est. Priority Date: 08/31/1978
• Status: Expired due to Term

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Miyasaka, Kiyoshi, Mogi, Junichi
• Primary Examiner(s): Edlow, Martin H.
• Application Number:
  US06/071,083
• Time in Patent Office: 529 Days
• Field of Search: 357/23, 357/41, 357/55
• US Class Current: 257/302
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H10B 12/34 the transistor being at least partially in a trench in the substrate

Abstract

A semiconductor device has VMOS transistors and VMOS dynamic memory cells which are formed on the same semiconductor substrate of a first conductivity type. A buried layer of the opposite conductivity type is formed between the substrate and an epitaxial layer having V-grooves for the VMOS dynamic memory cells. In the buried layer are formed buried layers of the first conductivity type serving as sources and capacitors for the VMOS dynamic memory cells.

Claims

1. A semiconductor device which has V-groove metal oxide semiconductor (VMOS) transistors and VMOS dynamic memory cells, comprising:

a lightly doped semiconductor single-crystalline substrate of a first conductivity type;

a semiconductor epitaxial layer of the opposite conductivity type formed selectively on said substrate, said epitaxial layer having V-grooves for the VMOS transistors and the VMOS dynamic memory cells and having heavily doped regions of the first conductivity type adjacent said V-grooves at the surface portions of said epitaxial layer;

an oxide layer formed on said V-grooves and epitaxial layer;

electrode layers formed on said oxide layer in said V-grooves;

a first heavily doped region of the first conductivity type formed in a first surface portion of said substrate, the bottom peaks of said V-grooves of said VMOS transistors reaching to said first heavily doped region; and

second heavily doped regions of the first conductivity type formed in a third heavily doped region of the opposite conductivity type, said third heavily doped region being formed in a second surface portion of said substrate, each bottom peak of said V-grooves of said VMOS dynamic memory cells reaching to a separate one of said second heavily doped regions

3. A semiconductor device according to claim 1 or 2, wherein said semiconductor single-crystalline substrate comprises silicon.

4. A semiconductor device according to claim 1 or 2, wherein said semiconductor epitaxial layer comprises silicon.

5. A semiconductor device according to claim 1 or 2, wherein said semiconductor single-crystalline substrate and said epitaxial layer comprises silicon and the surface of said semiconductor epitaxial layer in the (100) plane.

6. A semiconductor device according to claim 1 or 2, wherein said oxide layer comprises silicon dioxide.

7. A semiconductor device according to claim 1 or 2, wherein said electrode layers in said V-grooves comprises conductive polysilicon.

8. A semiconductor device according to claim 1 or 2, wherein said electrode layers in said V-grooves comprise aluminum metal.

2. A semiconductor device which has V-groove metal oxide semiconductor (VMOS) transistors and VMOS dynamic memory cells, comprising:

a doped semiconductor single-crystalline substrate of a first conductivity type;

a semiconductor epitaxial layer of the opposite conductivity type formed selectively on said substrate, said epitaxial layer having V-grooves for the VMOS transistors and the VMOS dynamic memory cells and having heavily doped regions of the first conductivity type adjacent said V-grooves at the surface portions of said epitaxial layer;

an oxide layer formed on said V-grooves and epitaxial layer;

electrode layers formed on said oxide layer in said V-grooves; and

at least one heavily doped region of the first conductivity type formed in a heavily doped region of the opposite conductivity type which is formed in a surface portion of said substrate, each bottom peak of said V-grooves of said VMOS dynamic memory cells reaching to a separate one of said heavily doped regions of said first conductivity type.