Redundant memory circuit

• US 4,250,570 A
• Filed: 01/09/1978
• Issued: 02/10/1981
• Est. Priority Date: 07/15/1976
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Hoff, Marcian E. Jr., Kannal, Gregory A., Tsang, Frederick
• Primary Examiner(s): Fears, Terrell W.
• Application Number:
  US05/867,779
• Time in Patent Office: 1,128 Days
• Field of Search: 365/200, 365/207, 365/210, 365/104, 365/105, 307/238
• US Class Current: 365/200
• CPC Class Codes: G11C 29/781 combined in a redundant decoder

Abstract

A redundant memory circuit for a memory array in which the memory has a preselected number of rows and columns having addresses associated therewith and decoders coupled thereto and one or more redundant rows or columns having initially unspecified addresses associated therewith and redundant decoders coupled thereto. The redundant memory circuit programs the redundant decoders coupled to the redundant rows or columns having initially unspecified addresses to match the addresses of defective rows or columns having addresses associated therewith and disables one or more of the defective rows or columns having addresses associated therewith.

Claims

1. A redundant memory circuit for a memory array comprising:

a memory having a preselected number of rows and columns having addresses associated therewith, each of said rows and columns having an individual decoder coupled thereto, and one or more redundant rows or columns having initially unspecified addresses associated therewith, each of said redundant rows or columns having an individual redundant decoder coupled thereto;

programming means for causing the redundant decoders coupled to said redundant rows or columns having initially unspecified addresses to respond only to the addresses of defective rows or columns having addresses associated therewith; and

means for disabling said defective rows or columns having addresses associated therewith.

2. The circuit of claim 1 wherein said means for disabling includes:

means for addressing a defective row or column;

fuse means coupled to said means for addressing and said row or column; and

means coupled to said fuse means and operable for allowing sufficient current to flow through said fuse means to blow said fuse means, whereby said defective row or column is disabled.

3. The circuit of claim 2 wherein said means coupled to said fuse means for allowing sufficient current to flow therethrough includes a transistor and means for enabling said transistor.

4. The circuit of claim 1 wherein said programming means includes:

a plurality of fuses coupled to each of said redundant decoders and operable to be selectively blown;

address means for applying to one or more of said redundant rows or columns the addresses of one or more of said defective rows or columns, coupled to said fuses; and

current means coupled to said fuses and coacting with said address means for allowing sufficient current to flow through selected ones of said fuses to blow said selected ones of said fuses.

5. The circuit of claim 4 wherein said current means includes a transistor and means for enabling said transistor.

6. The circuit of claim 4 wherein said address means includes a plurality of address buffers, each of said buffers having a single input and complementary outputs coupled to pairs of said fuses, whereby one of said pairs of fuses coupled to each address buffer is blown by the coaction of said address means and said current means.

7. The circuit of claim 6 wherein each of said address buffers includes a pair of series coupled inverters, each of said fuses being coupled to the output of one of said inverters.

8. The circuit defined by claim 4 wherein said fuses comprise silicon fusible links.

9. The circuit of claim 1 wherein said means for disabling includes means for disabling all of said rows or columns having addresses associated therewith when a programmed redundant row or column is addressed.

10. The circuit of claim 9 wherein said means for disabling also includes means for coupling said decoder of said redundant row or column to said decoders of said rows or columns having addresses associated therewith.

11. The circuit of claim 1 wherein said memory is a programmable read-only memory.

12. The circuit of claim 1 wherein said memory is a random access memory.