Method of making electroded wafer for electro-optic devices

• US 4,250,603 A
• Filed: 04/30/1979
• Issued: 02/17/1981
• Est. Priority Date: 04/30/1979
• Status: Expired due to Term

• Current Assignee: Aura Systems Inc.
• Original Assignee: Honeywell Incorporated (Honeywell International Inc.)
• Inventors: Luft, Victor
• Primary Examiner(s): Hall, Carl E.
• Application Number:
  US06/034,519
• Time in Patent Office: 659 Days
• Field of Search: 29/25.35, 310/365, 310/369, 350/356, 427/100, 427/123, 427/125, 427/304, 427/305
• US Class Current: 29/25.35
• CPC Class Codes: G02F 1/0551 Constructional details
• CPC Class Codes: Y10T 29/42 Piezoelectric device making

Abstract

An electroded wafer for use in electro-optic devices comprising a ceramic wafer having piezoelectric properties and having faces substantially larger than the thickness of the wafer. On the wafer are a plurality of parallel slots cut in at least one face of said wafer to form an interdigital matrix wherein adjacent slots are cut through the periphery of the wafer at opposite ends. Further included is a metallic electrode plated on the interior of the slots and the periphery of the wafer by electroless plating of at least one metal in contact with a palladium catalyzing compound such that the catalyzing compound is present only on the portions of the wafer to be plated.

Claims

1. A method of manufacturing an electroded wafer for use in electro-optic devices, comprising the steps of:

cutting a plurality of parallel slots in at least one face of a ceramic wafer having piezoelectric properties and having faces substantially larger than its thickness, said slots forming an interdigital matrix wherein adjacent slots are cut through the periphery of the wafer in opposing direction;

contacting said slotted wafer with a palladium catalyzing compound;

removing said catalyzing compound from the faces of said wafer; and

plating at least one metal on said wafer by electroless plating such that said metal adheres to said wafer on that portion of said wafer having the catalizing compound present.

2. The method of claim 1 which further includes the step of removing said catalyzing compound from two diametrically opposed portions of said periphery such that adjoining slots on said wafer are electrically insulated from one another.

3. The method of claim 1 wherein said metal is removed after plating from said wafer at two diametrically opposed portions of said periphery such that adjoining slots are electrically insulated from one another.

4. The method of claim 1 wherein the slots are from 75 to 99 percent of a full cut on said face.

5. The method of claim 1 wherein said slots have a ratio of depth to width ranging from 0.5/1 to 20/1.

6. The method of claim 1 wherein said slots range in thickness from about 1.0 mil to about 2.0 mils and the depth of said slots range from about 0.5 mil to about 20 mils.

7. The method of claim 1 wherein said wafer is plated by electroless plating of a quantity of nickel in a uniform thickness ranging from about 2 KA°

to 15 KA°

.

8. The method of claim 7 wherein an additional quantity of gold is plated on said nickel to a thickness to approximately 0.1 micrometers.