Digital cardiac pacemaker with refractory, reversion and sense reset means

• US 4,250,883 A
• Filed: 11/06/1978
• Issued: 02/17/1981
• Est. Priority Date: 11/06/1978
• Status: Expired due to Term

• Current Assignee: Med-El Incorporated
• Original Assignee: Medtronic Incorporated (Medtronic Plc)
• Inventors: Thompson, David L.
• Primary Examiner(s): Kamm, William E.
• Application Number:
  US05/957,962
• Time in Patent Office: 834 Days
• Field of Search: 128/419 PG, 128/419 PS, 128/419 PI
• US Class Current: 607/9
• CPC Class Codes: A61N 1/365 controlled by a physiological parameter, e.g. heart potential evoked response A61N1/371
• CPC Class Codes: A61N 1/37254 Pacemaker or defibrillator security, e.g. to prevent or inhibit programming alterations by hackers or unauthorised individuals

Abstract

A programmable cardiac pacemaker pulse generator utilizing digital circuitry for controlling the provision of cardiac stimulating pulses. The pulse generator is capable of having the rate, the pulse width, the pulse amplitude, the refractory period, the sensitivity and the mode of operation programmed. In addition, the pulse generator can have the output inhibited and can respond to programming signals causing a threshold margin test to be performed, effects of closure of the reed switch overridden, a hysteresis function added and a high rate exceeding the normal upper rate limit programmed. Many of the programmable functions of the pulse generator can either be programmed on a permanent or a temporary basis. The pulse generator further includes means for signaling the acceptance of a programming signal, and means to reset the program acceptance circuit if extraneous signals are detected as programming signlas. The program signal acceptance circuit performs several different checks on the detected programming signal including a parity check, an access code check and determining if the proper number of signals were transmitted within a given time. The timing circuit of the pulse generator includes a crystal clock oscillator and counter means for counting the clock pulses therefrom to determine the rate of the pacemaker. The pulse width of each pacemaker pulse is determined by using a voltage controlled oscillator in place of the crystal oscillator to obtain energy compensation due to the battery voltage decreasing with time.

Claims

1. A digital cardiac pacemaker pulse generator comprising:

a pair of output terminals, at least one of which is adapted to be electrically coupled through lead means to the heart;

sensing means for providing a signal manifesting the detection of electrical heart signals at said output terminals; and

digital control means including clock means for providing a series of clock signals, resettable counter means for counting said clock signals, output means responsive to said counter means reaching a certain count for providing an output signal to said terminals and reset means for resetting said counter means to an initial count, said reset means further comprising;

means coupled to said counter means for providing a first predetermined refractory count and a certain blank count of said counter means;

resettable fixed time measuring means which provides a signal a fixed time after being reset, said fixed time means being reset as a result of the provision of an output signal by said control means and further being reset by the occurrence of a sensing means signal after said certain blank time following said counter means being reset for resetting said counter means in response to said sensing means signal if said sensing means signal occurs after said first predetermined refractory count of said counter is reached and further if said sensing means signal occurs after the expiration of said fixed time measured from the last occurring one of an output signal or a signal provided by said sensing means after said certain blank count following the previous resetting of said counter means is reached.

2. The invention according to claim 1 wherein said reset means includes means for providing a signal each time said counter means reaches said first predetermined refractory count.

3. The invention according to claim 1 wherein said reset means includes means for providing a refractory signal each time said counter means reaches said first predetermined refractory count.

4. The invention according to claim 3 wherein said reset means further includes gate means responsive to said refractory signal and said time measuring means signal for providing an enable signal which enables said reset means to reset said counter means in response to said sensing means signal.

5. The invention according to claim 4 wherein said reset means further includes first and second settable bistable means, said first bistable means being set by the occurrence of said sensing means signal occurring after said certain blank time, and said second bistable means being set in response to the setting of said first bistable means and the provision thereto of said enable signal.

6. The invention according to claim 5 wherein said reset means further includes means for providing a blank signal after said counter means reaches a certain blank count.

7. The invention according to claim 6 wherein said reset means further includes second gate means responsive to said blank signal for enabling said first bistable means to be set by said sensing means signal only after said blank signal is provided.

8. The invention according to claim 7 wherein said first bistable means is reset in response to the resetting of said time measuring means.

9. The invention according to claim 8 wherein a signal indicating said time measuring means is reset is applied to said second gate means to cause said second gate means to provide a signal to reset said first bistable means.

10. The invention according to claim 9 wherein said reset means further includes gate means responsive to the resetting of said counter means and the setting of said first bistable means to provide a signal to reset said time measuring means.

11. The invention according to claim 10 wherein said gate means provides said signal to reset said time measuring means whenever either one of said counter means is reset or said first bistable means is set.

12. The invention according to claim 5 wherein said first bistable means is reset in response to the resetting of said time measuring means.

13. The invention according to claim 3 wherein said reset means further includes a first bistable circuit which is set upon the occurrence of said sensing means signal following said certain blank time.

14. The invention according to claim 13 wherein said reset means further includes means for providing a blank signal after said counter means reaches a certain blank count.

15. The invention according to claim 14 wherein said reset means further includes second gate means responsive to said blank signal for enabling said first bistable means to be set by said sensing means signal only after said blank signal is provided.

16. The invention according to claim 15 wherein said first bistable means is reset in response to the resetting of said time measuring means.

17. The invention according to claim 16 wherein a signal indicating said time measuring means is reset is applied to said second gate means to cause said second gate means to provide a signal to reset said first bistable means.

18. The invention according to claim 17 wherein said reset means further includes gate means responsive to the resetting of said counter means and the setting of said first bistable means to provide a signal to reset said time measuring means.

19. The invention according to claim 18 wherein said gate means provides said signal to reset said time measuring means whenever either one of said counter means is reset or said first bistable means is set.

20. A digital cardiac pacemaker pulse generator comprising:

a pair of output terminals, at least one of which is adapted to being electrically coupled through lead means to the heart;

digital control means including clock means for providing a series of clock signals at a fixed frequency, resettable counter means for counting said series of clock pulses and responsive to a counter reset signal for being reset to an initial count, counter reset means for providing said counter reset signal, and output means responsive to said counter reaching a certain count for providing an output signal to said terminals and for providing a signal to said counter reset means to cause said counter reset signal to be provided;

sensing means for providing a sense signal manifesting the detection of certain electric signals applied to said output terminals;

refractory means responsive to the count of said counter means for providing a refractory signal when said counter means reaches a certain refractory count after being reset;

blank signal means responsive to the count of said counter means for providing a blank signal from a time related to the resetting of said counter means until a time said counter means reaches a certain blank count, which blank count is less than said refractory count;

resettable fixed time means for providing a signal a certain fixed time after being reset;

sense reset means responsive to said sense signal, said refractory signal, said blank signal, and said time means signal for providing a signal to said counter means reset means to cause said counter to be reset whenever said sense signal occurs after the provision of said blank signal, said fixed time means signal and said refractory signal; and

fixed time reset means responsive to said sense signal occurring after said blank signal and said counter reset signal for resetting said fixed time means upon the occurrence of either said sense signal occurring after said blank signal or said counter reset signal.

21. The invention according to claim 20:

wherein said sense reset means includes first bistable means capable of assuming either a first state or a second state, said first bistable means further being maintained in said second state by said blank signal regardless of the provision thereto of said sense signal; and

wherein said fixed time reset means responds to said first bistable means going to said first state, by resetting said fixed time means.

22. The invention according to claim 21 wherein said sense reset means further includes gate means responsive to the application thereto of said blank signal and a signal indicating the resetting of said fixed time means for providing a signal to cause said first bistable means to assume said second state.

23. The invention according to claim 22 wherein said gate means provides said signal to cause said first bistable means to be in said second state as long as said blank signal is applied thereto.

24. The invention according to claim 21 wherein said fixed time reset means includes gate means responsive to the application thereto of a signal from said first bistable means and said counter reset signal for providing a signal to reset said fixed time means each time said first bistable means goes to said first state or said counter reset signal is provided.

25. The invention according to claim 24 wherein said sense reset means further includes second gate means responsive to the application thereto of said blank signal and a signal indicating the resetting of said fixed time means for providing a signal to cause said first bistable means to go to said second state.

26. The invention according to claim 24 wherein said second gate means provides said signal to cause said first bistable means to be in said second state as long as said blank signal is applied thereto.

27. The invention according to claim 21 wherein said sense reset means further includes second bistable means, said second bistable means being triggered from a first state to a second state in response to the occurrence of said first bistable means changing from said second to said first state as long as both said refractory signal and said time means signal have been provided.

28. The invention according to claim 27 wherein said counter reset means responds to said second bistable means going from said first to said second states by providing said counter reset signal.

29. The invention according to claim 28 wherein said second bistable means responds to said counter reset signal by going to said first state.

30. The invention according to claim 29 wherein said sense reset means further includes gate means for providing a signal to said second bistable means whenever both said refractory and time means signals have been provided thereto, the provision of said gate means signal and said first bistable means going from said second to said first state causing said second bistable means to go from said first to said second state.

31. The invention according to claim 30 wherein said sense reset means further includes second gate means responsive to the application thereto of said blank signal and a signal indicating the resetting of said fixed time means for providing a signal to cause said first bistable means to go to said second state.

32. The invention according to claim 31 wherein said second gate means provides said signal to cause said first bistable means to be in said second state as long as said blank signal is applied thereto.

33. The invention according to claim 32 wherein said fixed time reset means includes second gate means responsive to the application thereto of a signal from said first bistable means and said counter reset signal for providing a signal to reset said fixed time means each time said first bistable means goes to said first state or said counter reset signal is provided.

34. The invention according to claim 33 wherein said sense reset means further includes third gate means responsive to the application thereto of said blank signal and a signal indicating the resetting of said fixed time means for providing a signal to cause said first bistable means to go to said second state.

35. The invention according to claim 34 wherein said third gate means provides said signal to cause said first bistable means to be in said second state as long as said blank signal is applied thereto.

36. The invention according to claim 20 wherein said refractory means is programmable and includes means responsive to externally applied signals selecting one of a plurality of certain refractory counts at which said refractory signal is provided.

37. The invention according to claim 36 wherein said plurality of certain refractory counts includes any count, whereby the refractory period of said pulse generator is equal to said certain fixed time.

38. The invention according to claim 36 wherein said plurality of certain refractory counts includes no count, whereby said pulse generator operates in an asynchronous mode.