Dual channel capacitance measurement device
First Claim
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1. A dual channel capacitance measurement device providing a display of the capacitance of the device under test without the inclusion of stray capacitances, comprising:
- a. means for generating a train of clock pulses of known frequency;
b. means for generating a first time interval gate proportional to the capacitance of the device under test including stray capacitances;
c. means for generating a second time interval gate proportional to the said stray capacitances;
d. means for synchronizing the said first time gate means and the said second time gate by the said train of clock pulses;
e. means for subtracting the said second time interval gate from the said first time interval gate and providing a third time interval gate proportional to the capacitance of the device under test;
f. means cooperating with the said third time interval gate and the said train of clock pulses for gating a number of said clock pulses responsive to the said third time interval; and
g. means for counting and displaying the said number of gated clock pulses.
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Abstract
The capacitance of an unknown capacitor is determined by counting the cycles of a known frequency contained within a time gate whose time duration is determined by subtracting a gate whose length is equivalent to the stray measuring capacitance from a gate whose length is determined by the capacitance of the unknown capacitor plus the unavoidable stray measuring capacitances.
5 Citations
1 Claim
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1. A dual channel capacitance measurement device providing a display of the capacitance of the device under test without the inclusion of stray capacitances, comprising:
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a. means for generating a train of clock pulses of known frequency; b. means for generating a first time interval gate proportional to the capacitance of the device under test including stray capacitances; c. means for generating a second time interval gate proportional to the said stray capacitances; d. means for synchronizing the said first time gate means and the said second time gate by the said train of clock pulses; e. means for subtracting the said second time interval gate from the said first time interval gate and providing a third time interval gate proportional to the capacitance of the device under test; f. means cooperating with the said third time interval gate and the said train of clock pulses for gating a number of said clock pulses responsive to the said third time interval; and g. means for counting and displaying the said number of gated clock pulses.
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Specification
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Current AssigneeDonald M. Montana
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Original AssigneeDonald M. Montana
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InventorsMontana, Donald M.
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Primary Examiner(s)Karlsen, Ernest F.
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Application NumberUS05/937,021Time in Patent Office907 DaysField of Search324/60 C, 324/61 R, 324/60 CD, 324/60 RUS Class Current324/676CPC Class CodesG01R 27/2605 Measuring capacitance capac...
