Baseband differentially phase encoded radio signal detector

• US 4,253,067 A
• Filed: 12/11/1978
• Issued: 02/24/1981
• Est. Priority Date: 12/11/1978
• Status: Expired due to Term

• Current Assignee: Rockwell International Corporation
• Original Assignee: Rockwell International Corporation
• Inventors: Marston, Robert K., Caples, Edgar L., Massad, Khalil E.
• Primary Examiner(s): Grimm, Siegfried H.
• Application Number:
  US05/968,069
• Time in Patent Office: 806 Days
• Field of Search: 329/110, 329/117, 329/119, 329/122, 329/124, 329/50, 325/320, 325/344, 325/345, 325/346, 325/349, 455/214, 455/337, 375/80, 375/83-87
• US Class Current: 329/306
• CPC Class Codes: H04B 1/7093 Matched filter type

Abstract

A radio signal is applied to an in phase detector channel and a quadrature phase detector channel. Each detector channel includes, in cascade arrangement; an in phase downconverter means for downconverting the received radio signal to a baseband signal; a sampling means for sampling the baseband signal at a predetermined rate; and a matched filter means matched to the symbol waveform and wherein the sample pulses are stored over a predetermined period of time that corresponds to two data symbols. The sum of the pulses for the first data symbol and the sum of the pulses for the second data symbol are compared to determine if there has been a phase reversal between the two data symbols. The outputs of the in phase and quadrature phase channels are summed, which results in demodulation of the encoded data.

Claims

1. An apparatus for detecting differentially phase encoded radio signals, comprising:

a quadrature downconverter means for downconverting said differentially phase encoded radio signal to a first and second baseband signal in phase quadrature with each other;

first and second sampling means, each for providing on its output, a stream of pulses representative of an analog signal on its input;

means for applying said first baseband signal to said first sampling means;

means for applying said second baseband signal to said second sampling means;

first and second matched filter means,

means for connecting said first sampling means to said first matched filter means;

means for connecting said second sampling means to said second matched filter means;

timing means for periodically enabling said first and second sampling means and said first and second matched filter means; and

arithmetic means connected to said first and second matched filter means for subtracting the output of said second matched filter means from said first matched filter means whereby said differentially phase encoded ratio signal is detected.

2. The apparatus according to claim 1 wherein said quadrature downconverting means comprises:

first and second mixer means;

means for applying to said first mixer means a first mixing signal;

means for applying a second mixing signal that is in phase quadrature with said first mixing signal to said second mixer means;

first and second low pass filter means;

means for connecting said first low pass filter means to the output terminal of said first mixer means; and

means for connecting said second low pass filter means to the output terminal of said second mixer means.

3. The apparatus according to claim 2 wherein said means for applying a second mixing signal to said second mixer means comprises:

Hilbert'"'"'s transform means;

means for connecting said first mixing signal to an input terminal of said Hilbert'"'"'s transform means; and

means for connecting the output of said Hilbert'"'"'s transform means to said second mixer means.

4. The apparatus according to claim 1 wherein said quadrature downconverter means comprises:

a first and second mixer means;

a means for applying a mixing signal to said first and second mixer means;

a first and second low pass filter means;

means for connecting said first low pass filter means to said first mixer means;

means for connecting said second low pass filter means to said second mixer means; and

Hilbert'"'"'s transform means connected in line between said means for applying said radio signal to said quadrature downconverter means and said second mixer means whereby the output of said Hilbert'"'"'s transform means is in phase quadrature with said differentially phase encoded radio signal.

5. The apparatus according to claim 1 wherein said quadrature downconverter means comprises:

a first and second sample and hold device;

a first and second low pass filter means;

means for connecting said first low pass filter means to said first sample and hold device;

means for connecting said second low pass filter means to said second sample and hold device;

sampling control means for periodically energizing said sample and hold circuit wherein a sample of the signal present on the input of said sample and hold device is sampled and stored and presented on the output of said sample and hold device; and

Hilbert'"'"'s transform means inserted in line between said means for applying said radio signal to said quadrature downconverter means and said second sample and hold device whereby the output of said Hilbert'"'"'s transform means is in phase quadrature with said differentially phase encoded radio signal.

6. The apparatus according to claim 1 wherein said quadrature downconverting means comprises:

a first and second sample and hold device;

a first and second low pass filter means;

means for connecting said first low pass filter means to said first sample and hold device;

means for connecting said second low pass filter means to said second sample and hold device;

Hilbert'"'"'s transform means connected to said second sample and hold device; and

sampling control means connected to said first sample and hold circuit and said Hilbert'"'"'s transform means whereby said Hilbert'"'"'s transform means delays the output signal of said sampling control means to correspond to one quarter of a cycle of the carrier frequency of said radio signal and whereby the outputs of said first low pass filter means and said second low pass filter means are baseband signals in phase quadrature with each other.

7. The apparatus according to claim 1 wherein said differentially phase encoded radio signal is a coherent differentially phase encoded radio signal and said first and second matched filter means each comprises:

first matched filter device having an A section and a B section wherein each section stores and sums a first plurality of sample pulses; and

first multiplier means for multiplying the stored and summed output of said section A with the stored and summed output of said section B providing the product therefrom.

8. The apparatus according to claim 1 wherein said differentially phase encoded radio signal is a noncoherent differentially phase encoded radio signal and each of said first matched filter means and said second matched filter means comprises:

a first and second matched filter device each having an A section and a B section;

a first and second multiplier means wherein said first multiplier means is connected to the outputs of said A section and said B section of said first matched filter device and said second multiplier means is connected to said A section and said B section of said second matched filter device whereby said first multiplier means and said second multiplier means each multiplies the stored and summed outputs of said A section with the stored and summed outputs of said B section providing a product therefrom; and

means for connecting the outputs of said first and second matched filter devices to said arithmetic means for obtaining the combination of the products of said first multiplier means and the products of said second multiplier means of said first and second matched filter means.

9. The apparatus according to claim 8 wherein said differentially phase encoded ratio signal is a four phase differentially phase encoded radio signal and wherein said apparatus further comprises:

an inphase arithmetric means for summing the outputs of said first multiplier means of said first matched filter means and said first multiplier means of said second matched filter means whereby the inphase data is decoded therefrom; and

a quadrature arithmetic means for summing the product of said second multiplier means of said first and second matched filter means whereby the quadrature phase data is decoded therefrom.

10. The apparatus according to claims 7 or 8 wherein each of said first and second matched filter devices comprise:

a first charge transfer device having an A section and a B section with each section containing a symbol number of storage cells with each cell having a tapped output and wherein said symbol number is equal to the number of chips per symbol times the sample rate of said first and second sampling means;

a second arithmetic means having an A section and a B section, each section containing a sample symbol number of inputs which are summed and a resulting output obtained;

a plurality of coefficient weighting devices each having a preselected coefficient; and

means for connecting said preselected coefficient weighting devices between the tapped outputs of said charge transfer device and said inputs of said second arithmetic means whereby said connections being in a preselected order such that each of said matched filter devices is matched to a predetermined data symbol.

11. The apparatus of claims 7 or 8 wherein said matched filter device comprises:

a charge transfer device having an A section and a B section with each section containing at least a sample symbol number of storage cells with each cell having a tapped output and wherein said sample symbol number is equal to the number of chips per symbol times the sample rate of said first and second sample circuit;

a shift register means having an A section and a B section with each section containing at least a data symbol number of storge cells with each cell having a tapped output and wherein said data symbol number is equal to the number of chips per symbol;

a chip sequence generator which provides a continuous stream of data chips on its output terminal in a preselected order;

means for connecting said chip sequence generator to the input of said shift register means;

first clock source having a rate that corresponds to said sample rate;

means for connecting sid first clock source to a clock input terminal on said charge transfer device;

second clock source having a rate that is equal to said first clock rate source divided by the number of samples per chip;

means for connecting said second clock source to the clock input terminal of said shift register means;

first arithmetic means for providing the weighted summation of the outputs of said A section of said charge transfer device and said A section of said shift register means;

means for connecting said tapped outputs of said A section of said charge transfer device and said shift register means to said first arithmetic means;

second arithmetic means for providing the weighted summation of the outputs of said B section of said charge transfer device and said B section of said shift register means; and

means for connecting said tapped outputs of said B section of said charge transfer device and said shift register means to said second arithmetic means.

12. The apparatus according to claims 7 or 8 wherein each of said first and second multiplier means comprises:

a first arithmetic means for obtaining the summation of said A section and said B section of each of said matched filter devices;

a second arithmetic means for obtaining the summation of said A section and said B section of each of said matched filter devices;

a first squaring device connected to the output of said first arithmetic means for squaring said output of said first arithmetic means;

a second squaring device connected to the output of said second arithmetic means for squaring the output of said second arithmetic means; and

a third arithmetic means for obtaining the difference of the outputs of said first squaring device from the difference of the output of said second squaring device.

13. The apparatus according to claim 1 wherein each of said first matched filter means and said second matched filter means each comprises:

a chip matched filter device for obtaining the correlation between a first and second chip of said first or second baseband signal;

means for applying the first baseband signal to the input of the chip matched filter of the first matched filter means;

means for applying the second baseband signal to the input of the chip matched filter of the second matched filter;

a first inphase matched filter device matched to the inphase non-phase reversal chip code sequence;

a first quadrature phase matched filter device matched to the quadrature non-phase reversal chip code sequence;

a second inphase matched filter device matched to the phase reversal of the inphase chip code sequence;

a second quadrature matched filter device matched to the phase reversal of the quadrature chip code sequence;

means for connecting the output of the chip matched filter devices to the inputs of the first inphase matched filter device, the first quadrature phase matched filter device, the second inphase matched filter device, and the second quadrature matched filter device;

a first, second, third and fourth squaring device;

means for connecting said first squaring device to the output of said first inphase matched filter device;

means for connecting said second squaring device to the first quadrature matched filter device;

means for connecting said third squaring device to the output of said second inphase matched filter device;

means for connecting said fourth squaring device in the output of said second quadrature matched filter device;

a first arithmetic means for summing the outputs of said first squaring device of said first and second matched filter means;

means for connecting said first squaring device of said first and second matched filter means to said first arithmetic means;

a second arithmetic means for providing a summation of the outputs of said second squaring device of said first and second matched filter means;

means for connecting said second squaring device of said first and second matched filter means to said second arithmetic means;

a third arithmetic means for providing a summation of the outputs of said third squaring device of said first and second matched filter means;

means for connecting said third squaring device of said first and second matched filter means to said third arithmetic means;

a fourth arithmetic means for providing a summation of the outputs of said fourth squaring device of said first and second matched filter means;

means for connecting said fourth squaring device of said first and second matched filter means to said fourth arithmetic means;

a fifth arithmetic means for providing a summation of said first and second arithmetic means;

means for connecting said fifth arithmetic means to said first and second arithmetic means;

a sixth arithmetic means for providing a summation of the outputs of said third and fourth arithmetic means; and

means for connecting said sixth arithmetic means to said third and fourth arithmetic means.

14. The apparatus according to claim 13 wherein said chip matched filter device comprises:

a first charge transfer device having an A section and a B section with each section containing a chip number of storage cells wherein said chip number is equal to the number of sample pulses taken per chip;

a first and second summing device wherein each of said summing devices has a sample chip member of inputs which are summed with a resultant output;

a plurality of coefficient weighting devices, each device having a preselected coefficient; and

means for connecting each of said preselected coefficient weighting devices between a preselected output of said charge transfer device and a preselected input of said summing devices whereby each output of said charge transfer device is connected to the summing device by a member of said coefficient weighting devices.

15. The apparatus according to claim 13 wherein each of said first inphase matched filter devices, first quadrature matched filter devices, second inphase matched filter devices and second quadrature matched filter devices comprises:

a charge transfer device having an A section and a B section with each section containing a symbol number of storage cells wherein each symbol number is equal to at least one-half the number of chips per symbol;

a first and second summing device wherein each of said summing devices has a number of inputs which is equal to said symbol number;

a plurality of coefficient weighting devices each having a preselected coefficient; and

means for connecting each of said preselected coefficient weighting devices between a preselected output of said charge transfer device and a preselected input of said summing devices whereby each output of said charge transfer device is connected to the input of said summing devices by a member of said coefficient weighting devices.

16. The method of detecting a differentially phase encoded radio signal comprising the steps of:

quadrature downconverting a differentially phase encoded radio signal to a first and second baseband signal in phase quadrature with each other;

sampling said first and second baseband signal at a predetermined rate;

passing said sampled first baseband signal through a first matched filter device;

passing said sampled second baseband signal through a second matched filter device; and

combining the correlated output of said first matched filter device and said second matched filter device.

17. The method for detecting a differentially phase encoded ratio signal according to claim 16 wherein the step of passing said sampled baseband signals through said first and second matched filter devices each comprises the further steps of:

storing a first symbol of said baseband signal in a first storage device having a plurality of tapped outputs and storing a second symbol of said first baseband signal in a second storage device having a plurality of tapped outputs;

multiplying each output of said plurality of tapped outputs of said first storage device by a first group of predetermined coefficients obtaining a first plurality of weighted outputs;

multiplying each output of said plurality of tapped outputs of said second storage device by a second group of predetermined coefficients obtaining a second plurality of weighted outputs;

summing said first plurality of weighted outputs;

summing said second plurality of weighted outputs; and

multiplying the sum of said first plurality of weighted outputs with the sum of said second plurality of weighted outputs.

18. The method for detecting a differentially phase encoded radio signal according to claim 17 wherein the step of multiplying the sum of said first plurality of weighted outputs with the sum of said second plurality of weighted outputs, comprises:

obtaining a total summation by summing the sum of said first plurality of weighted outputs with the sum of said second plurality of weighted outputs;

obtaining a total difference by substracting from the sum of said first plurality of weighted outputs, the sum of said second plurality of weighted outputs;

squaring said total summation obtaining a squared total summation;

squaring said total difference obtaining a squared total difference; and

subtracting from said squared total summation, said squared total difference.