Memory unit with pipelined cycle of operations

• US 4,253,147 A
• Filed: 04/09/1979
• Issued: 02/24/1981
• Est. Priority Date: 04/09/1979
• Status: Expired due to Term

• Current Assignee: Rockwell International Corporation
• Original Assignee: Rockwell International Corporation
• Inventors: Richter, David L., MacDougall, James R.
• Primary Examiner(s): Malzahn, David H.
• Application Number:
  US06/028,621
• Time in Patent Office: 687 Days
• Field of Search: 364/200 MS File, 364/200
• US Class Current: 711/169
• CPC Class Codes: G06F 11/10 Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
• CPC Class Codes: G06F 11/2007 using redundant communication media
• CPC Class Codes: G06F 9/3875 Pipelining a single stage, e.g. superpipelining

Abstract

A memory unit is disclosed for receiving and executing instructions transmitted along buses. The memory unit includes registers and control logic that permit it to accept a second instruction from the bus and begin error checking procedures on the second instruction, all while completing the execution of a first instruction.

Claims

1. A memory unit for operating with first and second signal conductor buses, comprising:

means for executing a memory instruction;

means for accepting a first memory instruction from each of said buses and sending one of said first memory instructions to said means for executing, then accepting a second memory instruction from each of said buses before completion of the execution of the first memory instruction by said means for executing; and

means for performing, during said completion of the execution of the first memory instruction, the tasks of examining said second memory instructions as received on each of said buses and computing whether to utilize said second memory instruction as received on said first bus and whether to utilize said second memory instruction as received on said second bus.

2. A memory unit for executing instructions received from a bus, comprising:

at least one input register;

a plurality of additional registers, including a data register;

means including memory storage elements for executing an instruction including utilizing said additional registers;

control means for entering a portion of a word of a first instruction into said input register from said bus, for moving said first instruction word portion from the input register to one of said additional registers to be used by said means for executing, for entering a portion of a word of a second instruction into said input register from said bus, for causing said second instruction word portion to be held in said input register so long as the one of said additional registers appropriate to receive the held second portion is required for execution of the first instruction, and for preventing entering another portion of a word from said bus into the input register while the second instruction word portion is being held therein,

whereby the memory unit is capable of receiving a second instruction from the bus before completion of execution of a first instruction.

3. The memory unit of claim 2, additionally including means for beginning to check said second instruction word portion in said input register for errors, during said completion of the execution of said first instruction.

4. The memory unit of claim 2, wherein said first instruction includes a memory address and the one of said additional registers to which said first instruction word portion is moved is an address register.

5. The memory unit of claim 2, wherein said portion of a word of the first instruction is the second word of a multiple word instruction and includes data, and wherein the one of said additional registers to which said first instruction is moved is a data register.

6. The memory unit of claim 2, wherein said portion of a word of a second instruction includes a memory address and the one of said additional registers appropriate to receive the portion held in the input register is an address register.

7. The memory unit of claim 2, wherein said portion of a word of a second instruction is a second word of a multiple word instruction and includes data, and wherein said appropriate additional register is a data register.

8. Memory unit for executing instructions from a bus, each instruction including one or more words, comprising:

an input register;

a plurality of additional registers, including an address register and a data register;

means, including memory storage elements, for executing an instruction including utilizing said additional registers;

control means for entering a portion of a first word of a first instruction from said bus into said input register, then moving said portion from the input register to said address register, and if said first instruction includes a second word, for entering a portion of said second word from said bus into said input register and then moving said portion of said second word into said data register, for receiving a portion of a first word of a second instruction from said bus into said input register and then from the input register into said address register, for causing, upon receipt of a further portion which is a second word of said second instruction, said further portion to be entered from said bus into the input register and held in the input register so long as said data register is required for execution of the first instruction, and for preventing entering another portion of a word from said bus into the input register while said further portion is being held therein,

whereby the memory unit is capable of accepting a second instruction from the bus before completing the execution of a first instruction.