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Memory unit with pipelined cycle of operations

  • US 4,253,147 A
  • Filed: 04/09/1979
  • Issued: 02/24/1981
  • Est. Priority Date: 04/09/1979
  • Status: Expired due to Term
First Claim
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1. A memory unit for operating with first and second signal conductor buses, comprising:

  • means for executing a memory instruction;

    means for accepting a first memory instruction from each of said buses and sending one of said first memory instructions to said means for executing, then accepting a second memory instruction from each of said buses before completion of the execution of the first memory instruction by said means for executing; and

    means for performing, during said completion of the execution of the first memory instruction, the tasks of examining said second memory instructions as received on each of said buses and computing whether to utilize said second memory instruction as received on said first bus and whether to utilize said second memory instruction as received on said second bus.

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