Control apparatus for a transceiver employing a programmable memory

• US 4,254,504 A
• Filed: 08/08/1978
• Issued: 03/03/1981
• Est. Priority Date: 08/08/1978
• Status: Expired due to Term

• Current Assignee: Alcatel Network Systems India Limited (Nokia Corporation)
• Original Assignee: International Telephone and Telegraph Corporation
• Inventors: Carroll, James C., Lewis, James P.
• Primary Examiner(s): Bookbinder, Marc E.
• Application Number:
  US05/932,066
• Time in Patent Office: 938 Days
• Field of Search: 325/15, 325/17, 325/21, 325/25, 325/62, 325/144, 325/419, 325/422, 325/464, 325/187, 325/453, 325/459, 325/421, 325/457, 331/1 A, 331/15, 331/18, 331/25, 455/76, 455/77, 455/87, 455/173, 455/175, 455/176, 455/177, 455/179, 455/180, 455/183, 455/185, 455/186, 455/188, 455/200
• US Class Current: 455/76
• CPC Class Codes: H04B 1/40 Circuits

Abstract

A transceiver is controlled in operation by a programmable read only memory (PROM). The memory is accessed directly via a series of switches and when accessed, provides output data necessary to control the operation of the transceiver by controlling the frequency, the output power level and the mode of operation, as well as providing data to prevent transmission of unauthorized frequencies. The memory permits rapid and reliable programming of the apparatus enabling an untrained operator to use the equipment with reduced risk of unauthorized operation.

Claims

1. In a radio transceiver apparatus of the type capable of responding to any selected frequency contained within a band of operating frequencies by providing a local frequency signal indicative of said selected frequency, the combination therewith of apparatus for automatically controlling the operating characteristics of said transceiver apparatus, comprising:

memory means having a plurality of unique address locations, each location having stored therein a plurality of bits, with a first portion of said bits as stored indicative of a frequency of operation, and a second portion of said bits indicative of an operating power level, said memory having a plurality of data input lines for accessing any one of said address locations and a plurality of output lines for retrieving said plurality of bits stored at one of said address locations when accessed,

selectable switching means coupled to said data input lines to select said selected frequency by accessing a particular one of said address locations according to the setting of said switching means and to cause said memory means to provide said stored bits in said particular one of address locations on said output lines,

a programmable frequency source capable of providing any one of a plurality of local frequency signals, said source capable of providing said local frequency signal according to the application to control input lines associated with said source of said first portion of bits,

means for applying said first portion of said bits on said memory output lines to said control input lines of said frequency source to cause said source to provide said local frequency signal indicative of said selected frequency, and

means responsive to said second portion of bits on said memory output lines for controlling the transmitted output power level of said transceiver apparatus.

2. The apparatus according to claim 1 wherein said programmable frequency source comprises:

a variable oscillator capable of being tuned to any one of a plurality of output frequencies, said oscillator having a control input which upon application thereto of a first series of bits causes said oscillator to provide said any one frequency according to said series of bits,

a variable divider having an input coupled to said oscillator for providing an output frequency different from said oscillator frequency by a division factor, said divider having a control input for specifying any one of a number of division factors upon application to said divider control input of a second series of bits,

a reference oscillator capable of providing at an output a stable reference frequency,

means coupled to said oscillator and said divider for comparing said signals in frequency and to provide an error signal when the frequencies are not equal,

means coupled to said oscillator and responsive to said error signal for varying the frequency thereof in a direction to reduce said error signal,

means coupling a given number of said first portion of said bits to said control input of said oscillator to select said any one frequency,

means coupling the remainder of said first portion of said bits to said control input of said divider to select said factor and therefore to provide said different output frequency relatively equal to said reference frequency.

3. The apparatus according to claim 1 further comprising another switch having a first position indicative of a transmission mode and a second position indicative of a receive mode, said switch having an output coupled to one of said memory input data lines for accessing a first location during a receive mode and a second location during a transmit mode.

4. The apparatus according to claim 1 further comprising at least a third bit stored in memory and indicative of an unauthorized frequency and means responsive to the presence of said third bit to deactivate said apparatus.

5. Apparatus for controlling the frequency of operation of a transceiver by providing a local signal at a specified frequency indicative of any one frequency within a band of operation, comprising:

a frequency control loop including a variable controlled oscillator (VCO) capable of being tuned to any one of a plurality of frequencies, said variable oscillator having a control input for application thereto of a first number of bits indicative of a first frequency range, a divider having an input coupled to said oscillator and an output for providing a divided frequency signal, said divider having a control input adapted to receive a second number of bits for specifying a division factor selected according to said specified frequency to provide said divided signal within a specified range, a reference oscillator, comparison means coupled to said reference oscillator and said divider output to provide an error signal when the frequencies are different, and means for applying said error signal to said VCO to vary the frequency thereof according to said error signal,

rotary dial switching means for providing a first code of a predetermined number of bits less than the sum of said first and second number of bits, said first code specifying said any one frequency,

memory means having a plurality of unique address locations, said locations capable of having stored therein a number of words, each word consisting of a number of bits at least equal to the sum of said first and second number of bits, with a first portion of said word manifesting said first series of bits indicative of a frequency range for said VCO, and a second portion of said word manifesting a number of bits for specifying said division factor, said memory means having a plurality of input lines adapted to receive said first code for accessing any one of said address locations, with said input lines coupled to said switching means to cause said memory to provide said word at output lines associated with said memory,

means for coupling said first series of bits on said memory output lines to said control input of said VCO,

means for coupling said second series of bits on said memory output lines to said control input of said divider, and

a band select switch coupled to said data input lines of said memory and operative to access a first portion of said memory locations in a first position and a second portion of said memory locations in a second position.

6. Apparatus for controlling the frequency of operation of a transceiver by providing a local signal at a specified frequency indicative of any one frequency within a band of operation, comprising:

a frequency control loop including a variable controlled oscillator (VCO) capable of being tuned to any one of a plurality of frequencies, said variable oscillator having a control input for application thereto of a first number of bits indicative of a first frequency range, a divider having an input coupled to said oscillator and an output for providing a divided frequency signal, said divider having a control input adapted to receive a second number of bits for specifying a division factor selected according to said specified frequency to provide said divided signal within a specified range, a reference oscillator, comparison means coupled to said reference oscillator and said divider output to provide an error signal when the frequencies are different, and means for applying said error signal to said VCO to vary the frequency thereof according to said error signal,

rotary dial switching means for providing a first code of a predetermined number of bits less than the sum of said first and second number of bits, said first code specifying said any one frequency,

memory means having a plurality of unique address locations, said locations capable of having stored therein a number of words, each word consisting of a number of bits at least equal to the sum of said first and second number of bits, with a first portion of said word manifesting said first series of bits indicative of a frequency range of said VCO, and a second portion of said word manifesting a number of bits for specifying said division factor, said memory means having a plurality of input lines adapted to receive said first code for accessing any one of said address locations, with said input lines coupled to said switching means to cause said memory to provide said word at output lines associated with said memory,

means for coupling said first series of bits on said memory output lines to said control input of said VCO,

means for coupling said second series of bits on said memory output lines to said control input of said divider,

said memory having stored therein at a specified address a first portion of said word at a first address location and a second portion of said word at a second address location,

means responsive to the activation of said switching means to cause said memory to first provide said first portion of said word and then said second portion, and

means responsive to said memory operation for storing said first and second portions and therefore said entire word.

7. In a transceiver apparatus for enabling a user to receive and transmit automatically at the correct frequency and power levels, comprising:

a memory having a plurality of unique address locations, each location having stored therein predetermined number of bits indicative of a receive or transmit mode, with a first portion of said bits manifesting the frequency of operation and a second portion manifesting the power level, said memory having a plurality of data input lines for accessing any one of said locations and a plurality of output lines for retrieving said plurality of bits stored at said address,

first switching means coupled to a first predetermined number of said data input lines for specifying a portion of said address according to the desired frequency,

second switching means coupled to a second predetermined number of said data input lines for specifying a portion of said address according to a range of frequencies containing said desired frequency,

third switching means coupled to a third predetermined number of data input lines for specifying a portion of said address according to a transmit or receive mode of operation of said transceiver,

first means coupled to a first number of said memory output lines for providing a frequency within said range according to a selected portion of said first portion of said bits,

second means coupled to a second number of memory output lines for providing said correct frequency according to another selected portion of said first portion of bits,

third means coupled to a third number of memory output lines for providing a correct power level according to said second portion of bits.

8. The apparatus according to claim 7 wherein said first switching means comprises a BCD switch for selecting a channel indicative of said desired frequency.

9. The apparatus according to claim 7 wherein said second switching means comprises a two position switch for selecting a first or a second range of frequencies.

10. The apparatus according to claim 7 wherein said third switching means comprises a transmit-receive switch operative to implement a receive mode in a first position and a transmit mode in a second position.

11. The apparatus according to claim 7 wherein said first means includes a variable oscillator having an input control adapted to respond to said selected portion of said first portion of bits to provide a frequency at an output within said range.

12. The apparatus according to claim 11 wherein said second means includes a variable frequency divider coupled to said oscillator in a control loop, and having an input adapted to receive said another portion of said first portion of bits for specifying a division factor necessary to control said oscillator as contained in said loop.

13. The apparatus according to claim 7 wherein said third means includes a variable attenuator responsive to said second portion of bits for determining the output level during a transmission mode.

14. The apparatus according to claim 7 further comprising:

a bit counter having an output coupled to a fourth predetermined number of memory data input lines and responsive to the activation of any one of said first, second, or third switching means for causing said memory to provide said plurality of bits as stored in more than one of said addresses.

15. The apparatus according to claim 14 further comprising:

storage means coupled to said counter and operative to store the bits accessed from each memory location as retrieved.

16. A method of controlling the operation of a transceiver, comprising the steps of:

storing in a memory a plurality of bits at each of a given number of storage locations, with a first portion of said bits indicative of one frequency of a plurality of frequencies in a band of operation and a second portion of said bits indicative of an operating power level,

selecting one of said locations,

retrieving and storing said first portion of said bits during a first operation,

retrieving and storing said second portion of said bits during a second operation,

applying said first portion of said bits to a controllable frequency source to cause said source to provide said frequency according to said first bit content, and

applying said second portion of said bits to a power level control device to cause said power level control device to provide an output according to said second bit content.

17. The method according to claim 16 wherein the step of selecting said location includes selectively switching from a first one of said locations to another of said locations according to said one frequency selected.

18. The method according to claim 16 further including:

selecting a first series of locations during a transmission mode and selecting a second series of locations during a receive mode.