Thermally isolated monolithic semiconductor die

• US 4,257,061 A
• Filed: 10/17/1977
• Issued: 03/17/1981
• Est. Priority Date: 10/17/1977
• Status: Expired due to Term

• Current Assignee: John Fluke Mfg. Co., Inc.
• Original Assignee: John Fluke Mfg. Co., Inc.
• Inventors: Gurol, I. Macit, Chapel, Roy W. Jr.
• Primary Examiner(s): Wojciechowicz, Edward J.
• Application Number:
  US05/842,972
• Time in Patent Office: 1,247 Days
• Field of Search: 357/68, 357/69, 357/28, 357/55, 357/51, 357/49, 357/71
• US Class Current: 257/735
• CPC Class Codes: G01R 19/03 using thermoconverters
• CPC Class Codes: H01L 21/76264 SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
• CPC Class Codes: H01L 21/76289 Lateral isolation by air gap
• CPC Class Codes: H01L 21/764 Air gaps H01L21/76264 takes precedence
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/4823 connecting the wire to a pin of the item
• CPC Class Codes: H01L 2224/48472 the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/78 Apparatus for connecting with wire connectors
• CPC Class Codes: H01L 2224/85 using a wire connector
• CPC Class Codes: H01L 23/147 Semiconductor insulating substrates semiconductor conductive substrates H01L23/4926
• CPC Class Codes: H01L 23/4822 Beam leads
• CPC Class Codes: H01L 23/495 Lead-frames or other flat leads H01L23/498 takes precedence; lead frame interconnections between components H01L23/52
• CPC Class Codes: H01L 23/498 Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers shape of the substrate H01L23/13
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 24/85 : using a wire connector wire bonding in general B23K20/004
• CPC Class Codes: H01L 27/0211 : adapted for requirements of temperature
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01007 : Nitrogen [N]
• CPC Class Codes: H01L 2924/01011 : Sodium [Na]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01043 : Technetium [Tc]
• CPC Class Codes: H01L 2924/01045 : Rhodium [Rh]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/12033 : Gunn diode
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/19043 : being a resistor

Abstract

A process for producing thermally isolated monolithic semiconductor die and die produced by the process, plus improved apparatus using the die are disclosed. The process generally comprises the steps of: forming a desired semiconductor component or circuit in a semiconductor wafer (preferably a silicon wafer of <100> crystal orientation) having a protective layer (SiO₂) on one surface; forming platinum silicide contact windows in said protective layer where external connections to the semiconductor component or circuit is necessary; forming support leads of a layer of adhesive material (which also may have resistive properties, such as Nichrome) and a layer of a structurally strong metal of high electrical conductivity and low thermal conductivity (preferably 304 stainless steel) along predetermined paths extending outwardly toward the edge of the die from said contact windows; simultaneously with the forming of the adhesive layer of said support leads, forming one or more thin film resistors in predetermined regions of said die atop said SiO₂ protective layer, if desired; removing said SiO₂ protective layer from a region defined by said support leads, an island or islands in which said semiconductor component or circuit and said resistors are formed and a surrounding frame; and, removing said silicon from the region between said island or islands and said frame. The resulting semiconductor die comprises a frame surrounding one or more islands in which semiconductor components or circuits are formed, and which support resistors, if included. The islands are entirely supported by the support leads extending between the frame and the islands. In addition to providing support, the support leads also provide for electrical connection to the semiconductor components or circuits and to the resistors. The semiconductor die may be mounted in a package that also forms part of the invention. The package includes a ceramic substrate having an aperture in its center and alignment mesas and ridges on one surface. The ceramic substrate is formed so as to be mounted on the metal header of a conventional semiconductor canister housing. Depending upon their specific nature the resulting die are useful in and/or improve a variety of electrical apparatus. They are particularly useful as the dual RMS sensor element of an RMS converter. They can also be formed so as to be useful as radiation sensors. Or, they can be formed so as to provide a thermal platform whose temperature is controlled and stabilized at a predetermined value. All of these dies and the improved circuits resulting from their use also form part of the invention.

Claims

1. A thermally isolated monolithic semiconductor die comprising:

(a) semiconductor wafer including;

(1) a frame having an aperture formed therein; and

,

(2) at least one island located in said aperture in said frame, said island having formed therein a semiconductor item having a plurality of terminals; and

,

(b) a plurality of support leads, each of said support leads extending between said island and said frame and formed such that the island end of said support leads are each in contact with a predetermined one of the terminals of said semiconductor item, said support leads providing the sole support for said island, each of said support leads including a layer of a structurally strong metal of high electrical conductivity and low thermal conductivity, said layer of structurally strong metal being substantially thicker than any other layer of said support leads.

2. A thermally isolated monolithic semiconductor die as claimed in claim 1 wherein said semiconductor wafer is formed of silicon.

3. A thermally isolated monolithic semiconductor die as claimed in claim 2 wherein said silicon wafer has a <

100>

crystal orientation.

4. A thermally isolated monolithic semiconductor die as claimed in claim 3 wherein each of said support leads has a figure of merit of no less than 2,000, said figure of merit defined as tensile strength divided by thermal conductivity with tensil strength being given in terms of pounds per square inch and thermal conductivity being given in terms of BTU per square foot, hours, degrees Fahrenheit per foot.

5. A thermally isolated monolithic semiconductor die as claimed in claim 4 wherein the electrical resistivity of said support leads is 300 microhmcentimeters or less.

6. A thermally isolated monolithic semiconductor die as claimed in claim 5 wherein each of said support leads also includes an adhesive layer located between said layer of said structurally strong metal and said protective layer of said wafer where said support leads overlies said island and said frame.

7. A thermally isolated monolithic semiconductor die as claimed in claim 6 wherein said adhesive layer is formed of a resistive material.

8. A thermally isolated monolithic semiconductor die as claimed in claim 7 wherein said resistive material is nichrome and wherein said structurally strong metal layer of said support leads is formed of stainless steel.

9. A thermally isolated monolithic semiconductor die as claimed in claim 8 wherein said semiconductor item is a semiconductor circuit.

10. A thermally isolated monolithic semiconductor die as claimed in claim 8 wherein said semiconductor item is a semiconductor component.

11. A thermally isolated monolithic semiconductor die as claimed in claim 10 wherein said semiconductor component is a transistor.

12. A thermally isolated monolithic semiconductor die as claimed in claim 1 wherein each of said support leads has a figure of merit of no less than 2,000, said figure of merit defined as tensile strength divided by thermal conductivity with tensile strength being given in terms of pounds per square inch and thermal conductivity being given in terms of BTU per square foot, hours, degrees Fahrenheit per foot.

13. A thermally isolated monolithic semiconductor die as claimed in claim 12 wherein the electrical resistivity of said support leads is 300 microhmcentimeters or less.

14. A thermally isolated monolithic semiconductor die as claimed in claim 13 wherein each of said support leads also includes an adhesive layer located between said layer of said structurally strong metal and said protective layer of said wafer where said support leads overlies said island and said frame.

15. A thermally isolated monolithic semiconductor die as claimed in claim 14 wherein said adhesive layer is formed of a resistive material.

16. A thermally isolated monolithic semiconductor die as claimed in claim 15 wherein said resistive material is nichrome and wherein said structurally strong metal layer of said support leads is formed of stainless steel.

17. A thermally isolated monolithic semiconductor die as claimed in claim 1 wherein each of said support leads also includes an adhesive layer located between said layer of said structurally strong metal and said protective layer of said wafer where said support leads overlies said island and said frame.

18. A thermally isolated monolithic semiconductor die as claimed in claim 17 wherein said adhesive layer is formed of a resistive material.

19. A thermally isolated monolithic semiconductor die as claimed in claim 18 wherein said resistive material is nichrome and wherein said structurally strong metal layer of said support leads is formed of stainless steel.

20. A thermally isolated monolithic semiconductor die as claimed in claim 1 wherein said semiconductor item is a semiconductor circuit.

21. A thermally isolated monolithic semiconductor die as claimed in claim 1 wherein said semiconductor item is a semiconductor component.

22. A thermally isolated monolithic semiconductor die as claimed in claim 21 wherein said semiconductor component is a transistor.

23. A thermally isolated monolithic semiconductor die as claimed in claim 1 wherein:

said semiconductor wafer includes a second island located in said aperture in said frame and spaced from said first island, said second island having formed therein a second semiconductor item; and

,

said plurality of support leads include further support leads, one for each terminal of said second semiconductor item, said further support leads extending between said second island and said frame and formed such that the island end of said further support leads are each in contact with a predetermined one of the terminals of said second semiconductor item, said further support leads providing the sole support for said second island, each of said further support leads including a layer of a structurally strong metal of high electrical conductivity and low thermal conductivity.

24. A thermally isolated monolithic semiconductor die as claimed in claim 23 wherein said semiconductor wafer is formed of silicon.

25. A thermally isolated monolithic semiconductor die as claimed in claim 24 wherein said silicon wafer has a <

100>

crystal orientation.

26. A thermally isolated monolithic semiconductor die as claimed in claim 25 wherein each of said support leads has a figure of merit of no less than 2,000, said figure of merit defined as tensile strength divided by thermal conductivity with tensile strength being given in terms of pounds per square inch and thermal conductivity being given in terms of BTU per square foot, hours, degrees Fahrenheit per foot.

27. A thermally isolated monolithic semiconductor die as claimed in claim 26 wherein the electrical resistivity of said suppot leads is 300 microhmcentimeters or less.

28. A thermally isolated monolithic semiconductor die as claimed in claim 27 wherein each of said support leads also includes an adhesive layer located between said layer of said structurally strong metal and said protective layer of said wafer where said support leads overlie said islands and said frame.

29. A thermally isolated monolithic semiconductor die as claimed in claim 28 wherein said adhesive layer is formed of a resistive material.

30. A thermally isolated monolithic semiconductor die as claimed in claim 29 wherein said resistive material is nichrome and wherein said structurally strong metal layer of said support leads is formed of stainless steel.

31. A thermally isolated monolithic semiconductor die as claimed in claim 30 wherein said semiconductor items are semiconductor circuits.

32. A thermally isolated monolithic semiconductor die as claimed in claim 30 wherein said semiconductor items are semiconductor components.

33. A thermally isolated monolithic semiconductor die as claimed in claim 32 wherein said semiconductor components are transistors.

34. A thermally isolated monolithic semiconductor die as claimed in claim 23 wherein each of said support leads has a figure of merit of no less than 2,000, said figure of merit defined as tensile strength divided by thermal conductivity with tensile strength being given in terms of pounds per square inch and thermal conductivity being given in terms of BTU per square foot, hours, degrees Fahrenheit per foot.

35. A thermally isolated monolithic semiconductor die as claimed in claim 34 wherein the electrical resistivity of said support leads is 300 microhmcentimeters or less.

36. A thermally isolated monolithic semiconductor die as claimed in claim 35 wherein each of said support leads also includes an adhesive layer located between said layer of said structurally strong metal and said protective layer of said wafer where said support leads overlie said islands and said frame.

37. A thermally isolated monolithic semiconductor die as claimed in claim 36 wherein said adhesive layer is formed of a resistive material.

38. A thermally isolated monolithic semiconductor die as claimed in claim 37 wherein said resistive material is nichrome and wherein said structurally strong metal layer of said support leads is formed of stainless steel.

39. A thermally isolated monolithic semiconductor die as claimed in claim 23 wherein each of said support leads also includes an adhesive layer located between said layer of said structurally strong metal and said protective layer of said wafer where said support leads overlie said islands and said frame.

40. A thermally isolated monolithic semiconductor die as claimed in claim 39 wherein said adhesive layer is formed of a resistive material.

41. A thermally isolated monolithic semiconductor die as claimed in claim 40 wherein said resistive material is nichrome and wherein said structurally strong metal layer of said support leads is formed of stainless steel.

42. A thermally isolated monolithic semiconductor die as claimed in claim 23 wherein said semiconductor items are semiconductor circuits.

43. A thermally isolated monolithic semiconductor die as claimed in claim 23 wherein said semiconductor items are semiconductor components.

44. A thermally isolated monolithic semiconductor die as claimed in claim 43 wherein said semiconductor components are transistors.

45. A thermally isolated monolithic semiconductor die as claimed in claim 23 including:

a first thin film resistor formed on said at least one island so as to be in thermal communication with said semiconductor item formed therein;

a second thin film resistor formed on said second island so as to be in thermal communication with said second semiconductor item; and

,

still further support leads, one for each terminal of said first and second thin film resistors, said still further support leads extending between said islands and said frame and formed such that the island end of said still further support leads are each in contact with a predetermined end of one of said thin film resistors, said still further support leads including a layer of a structurally strong metal of high electrical conductivity and low thermal conductivity.

46. A thermally isolated monolithic semiconductor die as claimed in claim 45 wherein said semiconductor wafer is formed of silicon.

47. A thermally isolated monolithic semiconductor die as claimed in claim 46 wherein said silicon wafer has a <

100>

crystal orientation.

48. A thermally isolated monolithic semiconductor die as claimed in claim 47 wherein each said support leads has a figure of merit of no less than 2,000, said figure of merit defined as tensile strength divided by thermal conductivity with tensile strength being given in terms of pounds per square inch and thermal conductivity being given in terms of BTU per square foot, hours, degrees Fahrenheit per foot.

49. A thermally isolated monolithic semiconductor die as claimed in claim 48 wherein the electrical resistivity of said support leads is less than 300 microhmcentimeters.

50. A thermally isolated monolithic semiconductor die as claimed in claim 49 wherein each of said support leads also includes an adhesive layer located between said layer of said structurally strong metal and said protective layer of said wafer where said support leads overlie said islands and said frame.

51. A thermally isolated monolithic semiconductor die as claimed in claim 50 wherein said adhesive layer is formed of a resistive material, said resistive material also forming said first and second thin film resistors.

52. A thermally isolated monolithic semiconductor die as claimed in claim 51 wherein said resistive material is nichrome and wherein said structurally strong metal layer of said support leads is formed of stainless steel.

53. A thermally isolated monolithic semiconductor die as claimed in claim 52 wherein said semiconductor items are semiconductor circuits.

54. A thermally isolated monolithic semiconductor die as claimed in claim 52 wherein said semiconductor items are semiconductor components.

55. A thermally isolated monolithic semiconductor die as claimed in claim 54 wherein said semiconductor components are transistors.

56. A thermally isolated monolithic semiconductor die as claimed in claim 45 wherein each said support leads has a figure of merit of no less than 2,000, said figure of merit defined as tensile strength divided by the thermal conductivity with tensile strength being given in terms of pounds per square inch and thermal conductivity being given in terms of BTU per square foot, hours, degrees Fahrenheit per foot.

57. A thermally isolated monolithic semiconductor die as claimed in claim 56 wherein the electrical resistivity of said support leads is less than 300 microhmcentimeters.

58. A thermally isolated monolithic semiconductor die as claimed in claim 57 wherein each of said support leads also includes an adhesive layer located between said layer of said structurally strong metal and said protective layer of said wafer where said support leads overlie said islands and said frame.

59. A thermally isolated monolithic semiconductor die as claimed in claim 58 wherein said adhesive layer is formed of a resistive material, said resistive material also forming said first and second thin film resistors.

60. A thermally isolated monolithic semiconductor die as claimed in claim 59 wherein said resistive material is nichrome and wherein said structurally strong metal layer of said support leads is formed of stainless steel.

61. A thermally isolated monolithic semiconductor die as claimed in claim 45 wherein each of said support leads also includes an adhesive layer located between said layer of said structurally strong metal and said protective layer of said wafer where said support leads overlie said islands and said frame.

62. A thermally isolated monolithic semiconductor die as claimed in claim 61 wherein said adhesive layer is formed of a resistive material, said resistive material also forming said first and second thin film resistors.

63. A thermally isolated monolithic semiconductor die as claimed in claim 62 wherein said resistive material is nichrome and wherein said structurally strong metal layer of said support leads is formed of stainless steel.

64. A thermally isolated monolithic semiconductor die as claimed in claim 45 wherein said semiconductor items are semiconductor circuits.

65. A thermally isolated monolithic semiconductor die as claimed in claim 45 wherein said semiconductor items are semiconductor components.

66. A thermally isolated monolithic semiconductor die as claimed in claim 65 wherein said semiconductor components are transistors.

67. A thermally isolated monolithic dual RMS sensor semiconductor die comprising:

a frame formed of silicon having a <

100>

crystal orientation, said frame including an aperture;

a first island formed of silicon having a <

100>

crystal orientation located in said aperture and spaced from the edge of said aperture, said first island having formed therein a semiconductor component;

a first thin film resistor formed on said first island adjacent to said first semiconductor component so as to be in thermal communication therewith;

a second island formed of silicon having a <

100>

crystal orientation also located in said aperture in said frame and spaced from said frame and said first island, said second island including a second semiconductor component formed therein;

a second thin film resistor formed on said second island adjacent said second semiconductor component so as to be in thermal communication therewith; and

,

a plurality of support leads at least equal in number to the number of terminals defined by said first and second semiconductor components and said first and second thin film resistors, said support leads extending outwardly from said islands to said frames so as to provide the sole support for said islands, each of said support leads including a layer of a structurally strong metal of high electrical conductivity and low thermal conductivity, said layer of structurally strong metal being substantially thicker than any other layer within each of said support leads.

68. A thermally isolated monolithic dual RMS sensor semiconductor die as claimed in claim 67 wherein said support leads each have a figure of merit greater than 2,000, said figure of merit defined as tensile strength divided by thermal conductivity, with tensile strength given in terms of pounds per square inch and thermal conductivity given in terms of BTU per square foot, hours, degrees Fahrenheit per foot.

69. A thermally isolated monolithic dual RMS sensor semiconductor die as claimed in claim 68 wherein the electrical resistivity of said support leads is 300 microhm-centimeters or less.

70. A thermally isolated monolithic dual RMS sensor semiconductor die as claimed in claim 69 wherein each of said support leads includes an adhesive layer located between said layer of structurally strong metal of high electrical conductivity and low thermal conductivity.

71. A thermally isolated monolithic dual RMS sensor semiconductor die as claimed in claim 70 wherein said adhesive layer is formed of a resistive material and wherein said resistive material also forms said thin film resistors.

72. A thermally isolated monolithic dual RMS sensor semiconductor die as claimed in claim 71 wherein said resistive material is nichrome and wherein said layer of structurally strong metal of said support leads is stainless steel.

73. A thermally isolated monolithic dual RMS sensor semiconductor die as claimed in claim 72 wherein said first and second semiconductor components are transistors.

74. A thermally isolated monolithic dual RMS sensor semiconductor die as claimed in claim 73 wherein said transistors are NPN transistors.

75. A thermally isolated monolithic dual RMS sensor semiconductor die as claimed in claim 67 wherein each of said support leads includes an adhesive layer located between said layer of structurally strong metal of high electrical conductivity and low thermal conductivity.

76. A thermally isolated monolithic dual RMS sensor semiconductor die as claimed in claim 75 wherein said adhesive layer is formed of a resistive material and wherein said resistive material also forms said thin film resistors.

77. A thermally isolated monolithic dual RMS sensor semiconductor die as claimed in claim 76 wherein said resistive material is nichrome and wherein said layer of structurally strong metal of said support leads is stainless steel.

78. A thermally isolated monolithic dual RMS sensor semiconductor die as claimed in claim 77 wherein said first and second semiconductor components are transistors.

79. A thermally isolated monolithic dual RMS sensor semiconductor die as claimed in claim 78 wherein said transistors are NPN transistors.

80. A thermally isolated semiconductor package comprising:

a header including a platform having a generally flat surface;

a plurality of connecting pins passing through said header so as to lie generally orthogonal to said flat surface;

a ceramic substrate mounted on said generally flat surface of said platform, said ceramic substrate including an aperture extending outwardly from said flat surface of said platform;

a semiconductor die mounted on the side of said ceramic substrate opposed to the side mounted on said generally flat surface of said platform, said semiconductor die including a frame having an aperture formed therein, said frame mounted on said ceramic substrate such that said frame aperture is aligned with said aperture in said ceramic substrate, said semiconductor die further including at least one island located in said aperture in said frame, said island including a semiconductor item formed therein, said semiconductor die further including support leads extending between said frame and said island for supporting said island and providing electrical connection to said semiconductor item;

electrical connecting means extending from said leads in the region of said frame to said connecting pins; and

,

a top attached to said header for enclosing ceramic substrate and said semiconductor die.

81. A thermally isolated semiconductor package as claimed in claim 80 wherein said header is formed of metal and including insulation means for insulating said connecting pins from said header.

82. A thermally isolated semiconductor package as claimed in claim 81 wherein said top is formed of metal.

83. A thermally isolated semiconductor package as claimed in claim 82 including a lens mounted in said top so as to image radiation on said island of said semiconductor die.

84. A thermally isolated semiconductor package as claimed in claim 80 including a lens mounted in said top so as to image radiation on said island of said semiconductor die.

85. A thermally isolated semiconductor package as claimed in claim 80 wherein said semiconductor die includes:

(a) a second island mounted in said aperture in said frame and spaced from said first island, said second island including a second semiconductor item formed therein; and

, (b) support leads extending between said second island and said frame for supporting said second island and providing electrical connection to said second semiconductor item formed in said second island.

86. A thermally isolated semiconductor package as claimed in claim 85 including a lens mounted so as to image radiation onto one of said islands of said semiconductor die.

87. A thermally isolated semiconductor package as claimed in claim 85 wherein said semiconductor items formed in said islands are semiconductor components.

88. A thermally isolated semiconductor package as claimed in claim 87 wherein said semiconductor components are transistors.

89. A thermally isolated semiconductor package as claimed in claim 88 wherein said semiconductor components are formed on the side of said islands facing said aperture in said ceramic substrate.

90. A thermally isolated semiconductor package as claimed in claim 89 including a lens mounted so as to image radiation onto one of said islands of said semiconductor die.

91. A thermally isolated semiconductor package as claimed in claim 85 including a thin film resistor formed on each of said islands and support leads extending between the ends of said thin film resistors and said frame and further including electrical connecting means for connecting said support leads extending to said thin film resistors to selected ones of said plurality of connecting pins passing through said platform.

92. A thermally isolated semiconductor package as claimed in claim 91 wherein said semiconductor items formed in said islands are semiconductor components.

93. A thermally isolated semiconductor package as claimed in claim 92 wherein said semiconductor components are transistors.

94. A thermally isolated semiconductor package as claimed in claim 80 wherein the side of said ceramic substrate on which said semiconductor die is mounted includes means for rapidly and easily aligning said semiconductor die.

95. A thermally isolated semiconductor package as claimed in claim 94 wherein said alignment means comprises a pair of ridges extending parallel to one another on opposite sides of said aperture and a pair of mesas lying opposed to one another and along an axis that lies parallel to the axis defined by said alignment ridges.

96. A thermally isolated semiconductor package as claimed in claim 80 wherein said support beams are each formed of an adhesive layer and a layer of a structurally strong metal of high electrical conductivity and a low thermal conductivity.

97. A thermally isolated semiconductor package as claimed in claim 96 wherein said adhesive layer is formed of a resistive material.

98. A thermally isolated semiconductor package as claimed in claim 97 wherein said layer of resistive material is nichrome and said layer of structurally strong metal is stainless steel.