Microprocessor controlled digital detector

• US 4,258,423 A
• Filed: 12/05/1979
• Issued: 03/24/1981
• Est. Priority Date: 12/05/1979
• Status: Expired due to Term

• Current Assignee: United States Of America As Represented By The Secretary Of The Army (Government of the United States of America)
• Original Assignee: The United States Of America As Represented By The Secretary Of The Army
• Inventors: Lane, Richard A., Fronek, Donald K.
• Primary Examiner(s): Smith, Jerry
• Application Number:
  US06/100,685
• Time in Patent Office: 475 Days
• Field of Search: 364/481, 364/484, 307/233 R, 324/78 R, 324/78 D, 324/78 E, 324/78 F, 328/138, 328/140
• US Class Current: 702/70
• CPC Class Codes: G01R 19/0007 Frequency selective voltage or current level measuring measuring frequency G01R23/00; testing attenuation in line transmission systems H04B3/48; monitoring testing in transmission systems H04B17/00
• CPC Class Codes: G01R 23/167 with digital filters

Abstract

In the digital detector the center frequency and bandwidth of a digital fer is controlled by a microprocessor. Amplitude information for the original input signal may be preserved or a simple threshold of energy may be detected within a bandpass. The microprocessor scans a selected frequency spectrum by digitally changing the decoding data controlled by software. This detector in conjunction with a scanning algorithm permits data acquisition in addition to energy detection, data acquisition being the process of controlling an incoming signal within a bandpass by moving the center frequency and bandpass of the filter and generating a corresponding error signal as the feedback control signal.

Claims

1. A microprocessor controlled digital detector for detecting the presence of selected frequencies in an input signal comprising:

a microprocessor system having a plurality of inputs and outputs, a waveform shaping circuit having an input adapted to receive an input frequency signal and an output coupled to said microprocessor system, an analog-to-digital converter having an input coupled to receive said input frequency signal and an output coupled to said microprocessor system, a buffer coupled to receive an output from said microprocessor system and having an output indicative of the bandpass of said input signal, and a digital-to-analog converter having an input coupled to an output of said microprocessor system and having an output indicative of the amplitude of said input signal.

2. A microprocessor controlled digital detector as set forth in claim 1 wherein said microprocessor system comprises a microprocessor, a first interface means coupled between said microprocesser, said shaping circuit, and said analog-to-digital converter for directing input signals to said microprocessor;

and a second interface means coupled between said microprocessor, said buffer and said digital-to-analog converter for directing output signals from said microprocessor.

3. A microprocessor controlled digital detector as set forth in claim 2 wherein said microprocessor system further comprises a read only memory coupled to said microprocessor for programmably providing read only storage from memory to said microprocessor;

and a random access memory coupled to said microprocessor for providing input signal data storage for said microprocessor.

4. A microprocessor controlled digital detector as set forth in claim 3 wherein said first and second interface means are respective peripheral interface adapters.

5. In a microprocessor controlled digital detector for detecting the presence of a selectable frequency above a threshold value of amplitude, the method of detection comprising the steps of:

establishing preliminary, adjustable upper and lower band edge limits for a bandpass within a digital memory circuit;

detecting a continuous wave frequency input signal;

counting digital pulses indicative of the positive half cycle of said continuous wave frequency for obtaining a pulse count equivalent to the period of said frequency;

comparing the count of said digital pulses to said established band edge limits for determining whether the count lies below, within, or above said limits;

providing an output signal indicative of the upper and lower limits of said band edge; and

adjusting said limits incrementally and recomparing the pulse count to the band edge limits until said pulse count falls within said adjustable upper and lower limits.

6. The method of detecting the presence of a selectable frequency as set forth in claim 5 and comprising the further steps of:

adjusting said limits incrementally in the direction of said pulse count and recomparing the pulse count to the band edge limits until said pulse count falls within said upper and lower limits; and

providing an output signal indicative of the center frequency between said upper and lower band edge limits when said count falls between said limits.