Self-adaptive computer load control

• US 4,262,331 A
• Filed: 10/30/1978
• Issued: 04/14/1981
• Est. Priority Date: 10/30/1978
• Status: Expired due to Term

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Gaffney, John E. Jr., Isert, Irwin L., Freeland, Joseph W.
• Primary Examiner(s): Zache, Raulfe B.
• Application Number:
  US05/955,562
• Time in Patent Office: 897 Days
• Field of Search: 364/200 MS File
• US Class Current: 710/124
• CPC Class Codes: G06F 9/4837 time dependent

Abstract

A self-adaptive computer load control apparatus and method are disclosed for allocating servicing time by a Central Processing Unit (CPU) to several Peripheral Processing Units (PE) under processing overload conditions. Each PE contains registers for storing the value of an expected interval of time between consecutive service periods, for storing the time of commencement of the last service period, and for storing the time of commencement of the present service period. Each PE also includes a comparator for comparing the difference between the times of commencement of the last and present service periods with the value of the expected interval between consecutive service periods. A control word generator is included in each PE for specifying the number of processing steps to be performed by the CPU during the present service period for the respective PE'"'"'s. The number of processing steps specified has a first magnitude when the comparator determines that the difference between the commencement times is less than the expected time. The number of processing steps specified is made less by the control word generator when the difference in commencement times is greater than the expected time between consecutive service periods.

Claims

1. In a digital processing system including a central processing unit and a plurality of peripheral processing units, each respectively connected to said central processing unit by means of a communication path, the peripheral processing units sequentially sharing the resources of the central processing unit during sequentially polled, service periods for performing steps, wherein the improvement comprises:

means in each peripheral processing unit for storing the value of an expected interval of time between consecutive service periods for the respective peripheral processing unit;

means in each peripheral processing unit for storing the time of commencement of the last service period for the respective peripheral processing unit;

means in each peripheral processing unit for storing the time of commmencement of the present service period for the respective peripheral processing unit;

means in each peripheral processing unit connected to each of the above said means in the respective peripheral processing unit for comparing the difference between said time of commencement of the present service period and said time of commencement of the last service period with said value of an expected interval of time between consecutive service periods;

means in each peripheral processing unit connected to said comparing means and having an output connected to said central processing unit for generating a control word specifying the number of said processing steps to be performed by said central processing unit during the present service period for the respective peripheral processing unit;

said control word generating means regulating processing overload conditions for said central processing unit by outputting a control word specifying a first magnitude for said number of processing steps when said comparing means determines said difference in said commencement times to be less than said expected time and specifying a second magnitude for said number of processing steps, less than said first magnitude, when said comparing means determines said difference in said commencement times to be greater than said expected time for the respective peripheral processing unit;

whereby processing overload conditions for said central processing unit can be regulated by said plurality of peripheral processing units.

2. The apparatus of claim 1, which further comprises:

said peripheral processing units each having an associated relative priority for servicing by said central processing unit;

said means for generating a control word further including means for multiplying the value of said number of processing steps by a numerical value for said relative priority for the respective peripheral processing unit;

whereby relatively low priority ones of said plurality of peripheral processing units will receive servicing by said central processing unit under overload conditions.