Keyboard with an externally programmable repeat rate and repeat delay rate counter
First Claim
1. An electrical keyboard comprising a plurality of selectively operable keyswitch matrix elements each having an actuated state and an unactuated state, and output means for scanning and sensing the state of each of said keyswitch matrix elements in a sequential cyclic manner comprising a master counter of N count stages, wherein N is a number sufficiently large so that each keyswitch matrix element may be associated with a unique count of said master counter, output encoding means for producing an initial output code that is derived from the count of said master counter which is associated with a particular keyswitch matrix element that has been actuated, repeat means for selectively repeating said output code comprising timing means for controlling the delay between said initial output code and a repeated output code wherein said repeat means comprises a programmable delay timing counter having M serially-coupled counting stages wherein at least a plurality of said counting stages may be individually initially programmed, where M is selected in accordance with the range of the desired delay, gate encoding means for encoding preselected counts of said master counter in order to provide a separate gating signal for each stage of said delay timing counter which is capable of being programmed and gating means for controlling the selective programming of said programmable stages in accordance with said gating signals and upon the application of an externally supplied program permit signal to said gating means simultaneously with the application of said gating signals from said gate encoding means to said gating means.
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Abstract
An electronic keyboard is disclosed in which the keyboard matrix is scanned by an integrated circuit scanner which incorporates a programmable repeat rate and repeat delay rate counter. The repeat interval of a key is achieved by setting the repeat counter to a predetermined count value so that this repeat interval is obtained when a repeatable key has been depressed. The repeat delay rate interval is delayed by a count value that is set in the counter so that the repeat delay interval may be shortened when a repeatable key is held down for continued repeating of the code signal. In the keyboard an eight bit counter is utilized in which all eight bits can be used for the delay rate, but in all cases the four least significant bits are used for the repeat rate. Both the repeat rate and the delay rate are externally programmable during the same programming period, under the control of external processing equipment to which the keyboard is connected. External programming of the repeat rate and the repeat delay rate counter allows the keyboard to be produced at a reduced cost over microcomputer implemented keyboards.
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Citations
5 Claims
- 1. An electrical keyboard comprising a plurality of selectively operable keyswitch matrix elements each having an actuated state and an unactuated state, and output means for scanning and sensing the state of each of said keyswitch matrix elements in a sequential cyclic manner comprising a master counter of N count stages, wherein N is a number sufficiently large so that each keyswitch matrix element may be associated with a unique count of said master counter, output encoding means for producing an initial output code that is derived from the count of said master counter which is associated with a particular keyswitch matrix element that has been actuated, repeat means for selectively repeating said output code comprising timing means for controlling the delay between said initial output code and a repeated output code wherein said repeat means comprises a programmable delay timing counter having M serially-coupled counting stages wherein at least a plurality of said counting stages may be individually initially programmed, where M is selected in accordance with the range of the desired delay, gate encoding means for encoding preselected counts of said master counter in order to provide a separate gating signal for each stage of said delay timing counter which is capable of being programmed and gating means for controlling the selective programming of said programmable stages in accordance with said gating signals and upon the application of an externally supplied program permit signal to said gating means simultaneously with the application of said gating signals from said gate encoding means to said gating means.
Specification