Fault monitor for numerical control system

• US 4,263,647 A
• Filed: 02/07/1979
• Issued: 04/21/1981
• Est. Priority Date: 02/07/1979
• Status: Expired due to Term

• Current Assignee: Allen-Bradley Company (Rockwell Automation, Inc.)
• Original Assignee: Allen-Bradley Company (Rockwell Automation, Inc.)
• Inventors: Merrell, Gregory L., Bernhard, Theodore L.
• Primary Examiner(s): Malzahn, David H.
• Application Number:
  US06/009,938
• Time in Patent Office: 804 Days
• Field of Search: 364/101, 364/102, 364/119, 364/200 MS File, 364/900 MS File, 235/304, 371/48
• US Class Current: 700/7
• CPC Class Codes: G05B 19/4063 Monitoring general control system G05B19/4062 takes precedence
• CPC Class Codes: G05B 2219/34466 Bad circuits, watchdog, alarm, indication
• CPC Class Codes: G06F 11/0724 in a multiprocessor or a multi-core unit multiprocessors per se G06F15/80
• CPC Class Codes: G06F 11/0757 by exceeding a time limit, i.e. time-out, e.g. watchdogs
• CPC Class Codes: G06F 13/32 using combination of interrupt and burst mode transfer

Abstract

Associated with each processor in a multiprocessor numerical control system is a watchdog timer circuit which is periodically reset by its processor under normal operating conditions. If a malfunction should occur in one of the processors, its watchdog timer is not reset and it times out. A fault monitor line connects to each watchdog timer circuit and an emergency stop circuit, and when a malfunction occurs in any one of the processors, this condition is indicated to all the processors and to the emergency stop circuit.

Claims

1. In a numerical control system having a plurality of separately operating programmed processors which operate together to control a machine tool, the improvement therein comprising:

a set of watchdog timer circuits, one associated with each of said processors and each watchdog timer circuit having an input terminal which periodically receives a signal from its associated processor that resets the watchdog timer and each having an output terminal at which a fault indicating logic signal is generated when the watchdog timer is not reset by its associated processor within a preset time interval;

a fault monitor line coupled to the output terminal of each of said watchdog timer circuits; and

an emergency stop circuit coupled to said fault monitor line and being operable to indicate a malfunction condition when any one of said watchdog timer circuits generates a fault indicating logic signal.

2. The improved numerical control system as recited in claim 1 in which said fault monitor line is coupled to each of said processors through means for interrupting the normal operation of said processors when a fault indicating logic signal is generated on the fault monitor line.

3. The improved numerical control system as recited in claim 2 in which each programmed processor includes a memory which stores a watchdog timer interrupt service routine when it is interrupted by the fault indicating logic signal on said fault monitor line.

4. The improved numerical control system as recited in claim 1, 2 or 3 in which said emergency stop circuit includes a relay having a coil which is energized when the fault indicating logic signal is not present on said fault monitor line and which is deenergized when the fault indicating logic signal is present.

5. In a numerical control system having a plurality of separately operating programmed processors which operate together to control a machine tool, the improvement therein comprising:

a set of fault detecting circuits, one associated with each of said processors and each fault detecting circuit being operable to generate a fault indicating logic signal at its output when a malfunction in its associated processor is detected;

means connecting the output of each fault detecting circuit to an interrupt request terminal on its associated processor; and

a fault monitor line coupled to the output terminal of each fault detecting circuit to apply a fault indicating logic signal generated by any one of said fault detecting circuits to the output terminals of all said fault detecting circuits,

wherein the generation of a fault indicating logic signal by any one of said fault detecting circuits causes an interrupt request signal to be applied to the interrupt request terminal on each processor in the numerical control system.

6. The improved numerical control system as recited in claim 5 in which each processor is responsive to an interrupt request signal applied to its interrupt request terminal to terminate performance of its current function and perform a preselected function.

7. The improved numerical control system as recited in claim 5 or 6 in which an emergency stop circuit is coupled to said fault monitor line and is operable to indicate a malfunction condition when any one of said fault detecting circuits generates a fault indicating logic signal.