Split system bus cycle for direct memory access of peripherals in a cathode ray tube display system

• US 4,263,648 A
• Filed: 12/26/1978
• Issued: 04/21/1981
• Est. Priority Date: 12/26/1978
• Status: Expired due to Term

• Current Assignee: Honeywell Information Systems, Inc. (Honeywell International Inc.)
• Original Assignee: Honeywell Information Systems, Inc. (Honeywell International Inc.)
• Inventors: Stafford, John P., Slater, Richard A., Ryan, Joseph L., Kobs, Frederick E.
• Primary Examiner(s): Thesz, Joseph M.
• Assistant Examiner(s): Chan, Eddie
• Application Number:
  US05/973,290
• Time in Patent Office: 847 Days
• Field of Search: 364/200 MS File, 364/900 MS File, 307/269, 328/59, 328/63
• US Class Current: 710/25
• CPC Class Codes: G06F 13/287 Multiplexed DMA G06F13/30 takes precedence
• CPC Class Codes: G09G 2360/12 Frame memory handling
• CPC Class Codes: G09G 2360/18 Use of a frame buffer in a display terminal, inclusive of the display panel
• CPC Class Codes: G09G 5/001 Arbitration of resources in a display system, e.g. control of access to frame buffer by video controller and/or main processor
• CPC Class Codes: G09G 5/363 Graphics controllers

Abstract

Apparatus in a Cathode Ray Tube (CRT) display allows the sharing of the system bus between the microprocessor (CPU) and Direct Memory Access (DMA) devices without degrading the CPU performance by splitting the system bus cycle into an address phase and a data phase.

Claims

1. A method for generating a split bus timing cycle in a terminal system having:

a system bus including a control bus, an address bus and a data bus;

a memory subsystem coupled to said system bus;

a central processor subsystem coupled to said system bus and to said memory subsystem;

a plurality of peripheral subsystems coupled to said system bus and to said memory subsystem;

timing means, coupled to said control bus including;

a clock generator;

a shift register;

a plurality of storage elements;

said method comprising the steps of;

a. generating successive clocking signals as an output of said clock generator;

b. applying said successive clocking signals to said shift register;

c. generating a plurality of first and second shift register signals from said shift register stages, each of said plurality of shift register signals being in a first state for a first predetermined number of said clocking signals and being in a second state for a second predetermined number of clocking signals;

d. setting a first storage element when said first of said shift register signals is in a first state and resetting said first storage element when said first of said shift register signals is in a second state, said first storage element setting and resetting on the rise of said clocking signals;

e. setting a second storage element when said second of said shift register signals is in a first state and resetting said second storage element when said second of said shift register signals is in a second state on the rise of said clocking signals;

f. applying the output of said first storage element to said central processor subsystem when said first storage element is reset and applying the output of said first storage element to said plurality of peripheral subsystems when said first storage element is set;

g. applying the output of said second storage element to said central processor subsystem when said second storage element is set and applying the output of said second storage element to said plurality of peripheral subsystems when said second storage element is reset;

h. gating said central processor subsystem address signals by the output of said first storage element when said first storage element is set thereby generating an address bus CPU cycle.

i. gating said plurality of peripheral subsystem address signals by the output of said first storage element when said first storage element is reset thereby generating an address bus DMA timing cycle;

j. gating the signals representative of a data transfer between said central processor subsystem and said main memory subsystem by the output of said second storage element when said second storage element is reset thereby generating a data bus CPU timing cycle;

k. gating the signals representative of a data transfer between one of said plurality of peripheral subsystems and said main memory subsystem by the output of said second storage element when said second storage element is set thereby generating a data bus DMA timing cycle;

i. applying said second shift register signal in said first state and a second phase timing signal in a second state to a first AND gate for generating a first phase timing signal in a first state for defining a CPU phase timing cycle, wherein said address bus DMA timing cycle and said data bus DMA timing cycle overlap said CPU phase timing cycle; and

,

m. applying said second shift register signal in said second state and said first phase timing signal in a second state to a second AND gate for generating said second phase timing signal in a first state, said second phase timing signal in said first state being applied to said first AND gate for generating said first phase timing signal in a second state for defining a DMA phase timing cycle, wherein said address bus CPU timing cycle and said data bus CPU timing cycle overlap said DMA phase timing cycle.

2. The method of claim 1 wherein said split bus cycle timing is generated by:

a. setting said first storage element with said first shift register signal in said first state for generating said address bus CPU cycle and resetting said second storage element with said second shift register signal in said second state for generating said data bus CPU cycle, said second shift register signal lagging said first shift register signal by 305 nanoseconds; and

,

b. resetting said first storage element with said first shift register signal in said second state for generating said address bus DMA cycle, and setting said second storage element with said second shift register signal in said first state for generating said data bus DMA cycle.