Digital data processing system with interface adaptor having programmable, monitorable control register therein
First Claim
1. A digital data processing system comprising:
- processor means for executing a plurality of instructions, said processor means generating control information in response to execution of a first one of said instructions, generating a write signal in response to execution of a second one of said instructions, and generating a read signal in response to execution of a third one of said instructions;
a bidirectional data bus coupled to said processor means;
memory means coupled to said processor means via said bidirectional data bus for storing said instructions and for storing data;
a peripheral data bus for coupling a peripheral device controlled by said digital data processing system to said digital data processing system; and
adaptor means coupled between said peripheral data bus and said bidirectional data bus for effecting transmittal of information between said peripheral device and said digital data processing system, said adaptor means comprising;
(1) control register means for storing said control information in response to said write signal and for sending a representation of said stored control information to said processor means in response to said read signal; and
(2) interface means coupled to said peripheral data bus and responsive to said control information stored in said control register means for sending data to and receiving data from said peripheral device.
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Abstract
A digital system including a plurality of metal-oxide-semiconductor (MOS) chip random access memories (RAM), read only memories (ROM) and peripheral interface adaptors coupled to a common bidirectional data bus which is coupled to and controlled by a microprocessor unit (MPU). Each peripheral interface adaptor includes a control register loadable under program control. The contents of the control register control selection of several registers within the interface adaptor. The control register also controls other functions of the peripheral interface adaptor, including determining direction of data movement at the peripheral buffers of the interface adaptor. The contents of the control register of each interface adaptor are monitorable by the microprocessor unit.
110 Citations
6 Claims
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1. A digital data processing system comprising:
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processor means for executing a plurality of instructions, said processor means generating control information in response to execution of a first one of said instructions, generating a write signal in response to execution of a second one of said instructions, and generating a read signal in response to execution of a third one of said instructions; a bidirectional data bus coupled to said processor means; memory means coupled to said processor means via said bidirectional data bus for storing said instructions and for storing data; a peripheral data bus for coupling a peripheral device controlled by said digital data processing system to said digital data processing system; and adaptor means coupled between said peripheral data bus and said bidirectional data bus for effecting transmittal of information between said peripheral device and said digital data processing system, said adaptor means comprising; (1) control register means for storing said control information in response to said write signal and for sending a representation of said stored control information to said processor means in response to said read signal; and (2) interface means coupled to said peripheral data bus and responsive to said control information stored in said control register means for sending data to and receiving data from said peripheral device. - View Dependent Claims (2, 3, 4, 5, 6)
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Specification