Distributed function communication system for remote devices

• US 4,264,954 A
• Filed: 09/04/1979
• Issued: 04/28/1981
• Est. Priority Date: 09/04/1979
• Status: Expired due to Term

• Current Assignee: NCR Corporation
• Original Assignee: NCR Corporation
• Inventors: Briggs, Barry D., Beason, George C.
• Primary Examiner(s): Shaw, Gareth D.
• Assistant Examiner(s): Heckler, Thomas M.
• Application Number:
  US06/071,896
• Time in Patent Office: 602 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 710/4
• CPC Class Codes: G06F 13/124 where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
• CPC Class Codes: G06F 13/22 using successive scanning, e.g. polling G06F13/24 takes precedence
• CPC Class Codes: G06F 13/4213 with asynchronous protocol

Abstract

To effect an accurate transmission of data between processing equipment and a plurality of peripheral devices, first and second interfaces are employed for reconstructing and transmitting the data over a communications link such as a conductor pair. The first interface termed a master terminal which is coupled to a common control module by way of a common control bus, receives instruction, address, and data information from the processor, and transmits a serial data code containing all this information to a plurality of second interfaces, termed slave terminals. Each slave terminal is coupled to a set of peripheral devices by a common bus and when a peripheral device recognizes its address being present in the code received from the master terminal, the slave terminal responds to complete the transaction with the master terminal and the addressed peripheral device.

Claims

1. A communications system for transmitting data between a data processor and a plurality of peripheral devices controlled by said processor comprising;

first interface means coupled over a first common bus to said processor and responsive to data transmission instructions including bus control signals and the address of a prescribed peripheral device supplied over said first common bus from the processor for generating a data code in accordance with the received data transmission instruction and which identifies the address of the peripheral device and the type of transaction to be carried out between said processor and said addressed peripheral device;

second interface means coupled over a second common bus to said plurality of peripheral devices addressable by said processor;

a transmission line connected between said first and second interface means;

said first interface means includes a first storage means for storing the data transmission instructions received from the processor over the first common bus and for outputting the data code when enabled;

first means for generating a transmission clock;

first circuit means responsive to receiving said bus control signals for generating a control signal;

first means coupled to said first clock generating means and said first circuit means for transmitting the data code at said transmission clock rate from said first storage means to said second interface means over said transmission line in response to the generation of said first control signal;

said second interface means includes means coupled to said transmission line for reconstructing said transmission clock from the transmitted data code;

second storage means coupled to said transmission line and said second common bus for storing the data code received from said first interface means;

second circuit means coupled to said second storage means and said second common bus for reconstructing from said transmitted data said bus control signals;

and third circuit means coupled to said second storage means and said clock reconstructing means for enabling said second storage means to output to the addressed peripheral device over said common bus said data code wherein the first and second interface means are transparent to the addressed peripheral device.

2. The communication system of claim 1 in which said first interface means includes fourth circuit means coupled to said first common bus and responsive to receiving said bus control signals for outputting over said first common bus a signal which inhibits a processing operation by said data processor during the transmission of data between the data processor and the addressed peripheral device.

3. The communication system of claim 1 in which said first circuit means includes first gating means responsive to receiving the address of the prescribed peripheral device enabling said transmission clock to transmit the data code from said first storage means to said second interface means when the address of the peripheral device is contained within only a preselected number of addresses available to be addressed by said processor.

4. The communications system of claim 1 in which said transmission line comprises a twisted pair of conductors, said first transmitting means is coupled to said first storage means and said first transmission clock generating means for transmitting the data code stored in said first storage means over the twisted pair of conductors at the rate of said transmission clock, and said second interface means includes a first receiver means coupled to said pair of conductors for receiving the data code transmitted by said first trans transmitting means, said receiver means includes said clock reconstructing means for reconstructing from the data code a clock signal corresponding to the transmission rate at which said data code is transmitted by said first transmitting means, said reconstructed clock enabling said second storage means to store said data code.

5. The communication system of claim 4 in which said second circuit means includes a plurality of bi-stable means coupled to said second storage means for reconstructing said common bus control signals in response to the storing of said data code in said second storage means.

6. The communication system of claim 5 in which said second storage means includes an address register for outputting the address of the prescribed peripheral device in said data code to the peripheral device and a data register for storing the data received from the prescribed peripheral device, said second interface means further including fifth circuit means responsive to a signal from the prescribed peripheral device whose address was outputted by said address register for transmitting the data stored in said data register to said first interface means.

7. The communication system of claim 6 in which said second interface means includes second means for generating said transmission clock, said second clock generating means coupled to said data register enabling said transmission clock to transmit the data code stored in said data register and received from the prescribed peripheral device to said first interface means.

8. A communications system for transmitting data between a data processor and a plurality of peripheral devices controlled by said processor comprising:

first adapter means coupled over a first common bus to said processor and responsive to parallel data transmission instructions including bus controls signals and the address of the prescribed peripheral device supplied over said first common bus from the processor for generating a serial data code in accordance with the received data transmission instructions and which includes the address of the prescribed peripheral device, the type of transaction and a data portion;

a plurality of second adapter means coupled over a second common bus to said plurality of peripheral devices addressable by said processor;

a twisted pair of conductors connected between said first adapter means and each of said second adapter means;

said first adapter means includes a first storage means coupled to said first common bus for storing said parallel data instructions and for outputting over said pair of conductors said serial data code when enabled;

first means coupled to said first storage means for generating a transmission clock;

first circuit means coupled to said first common bus and responsive to receiving said bus controls signals for enabling said transmission clock to clock said serial code from said first storage means over said twisted pair of conductors to each of said second adapter means;

each of said second adapter means includes means coupled to said twisted pair of conductors for reconstructing said transmission clock from the serial data code transmitted over said pair of conductors;

second storage means coupled to said pair of conductors for storing the address of the prescribed peripheral device, said second storage means further coupled to said reconstructing means and said second common bus for supplying over said second common bus at said recovered transmission clock rate the address of the prescribed peripheral device to the peripheral devices;

third storage means coupled to said clock reconstructing means for storing the data portion of the serial data code;

second circuit means coupled to said second storage means and said second common bus for reconstructing from the transmitted serial data code signal bus control signals;

and third circuit means coupled to said second and third storage means and said clock reconstructing means for enabling said third storage means to output in parallel said data portion to the addressed peripheral device over said second common bus in response to receiving the serial data code wherein the first and second adapters are transparent to the addressed peripheral device.

9. The communication system of claim 8 in which the data transmission instructions include a first data bit indicating the type of instruction supplied by the processor and said first adapter means includes fourth circuit means coupled to said first common bus and responsive to receiving said bus control signals and said data bit for outputting over said first common bus an inhibiting signal which inhibits a processing operation by said data processor during the transmitting of data between the data processor and the addressed peripheral device.

10. The communication system of claim 9 in which said first adapter means includes counter means operated in response to the outputting of the serial data code from said first storage means for terminating said inhibiting signal upon the expiration of a prescribed period of time.

11. The communication system of claim 8 in which said first circuit means includes gating means operated in response to receiving said bus control signal and the address of the prescribed peripheral device for allowing said transmission clock to enable said first storage means to output said serial data code to each of said second adapter means when the address of the peripheral device is contained within only a preselected number of addresses available to be addressed by said data processor.

12. The communication system of claim 8 in which said first adapter means includes a first transmitter means coupled to said first storage means and said first transmission clock generating means for transmitting the serial data code stored in said first storage means over the pair of conductors at the rate of said transmission clock to said second adapter, and each of said second adapter means includes a first receiver means coupled to said pair of conductors for receiving the serial data code transmitted by said first transmitting means and said second and third storage means, said receiver means including differentiator means and a one-shot multivibrator for reconstructing from the serial data code the transmission clock, and transmitting said clock to said second and third storage means whereby said recovered clock enables said second and third storage means to store said serial data code.

13. The communication system of claim 12 in which each of said second adapter means includes second means for generating said transmission clock, said second adapter means further including second transmitter means coupled to said third storage means, said second transmission clock generating means and said pair of conductors for transmitting data received from said addressed peripheral device and stored in said third storage means over the pair of conductors to said first adapter means at said transmission clock, and said first adapter means includes second receiver means for receiving the data transmitted by said second transmitter means, said second receiver means including second means for reconstructing the transmission clock from the transmitted data for use in transmitting the data to the data processor over the first common bus.

14. The communication system of claim 13 wherein said first and second transmitter means are structurally the same.

15. The communication system of claim 14 wherein said first and second receiver means are structurally the same.

16. The communication system of claim 15 in which each of said second adapter means includes fourth circuit means responsive to a second signal from the peripheral device whose address was stored in said second storage means for enabling said second transmission clock to output the data stored in said first storage means to said second transmitter means.